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Cypress Semiconductor |
CY7C02732 K / 64 K × 16 Dual-Port Static RAM
CY7C027
CY7C028
32 K / 64 K × 16 Dual-Port Static RAM
32 K / 64 K × 16 Dual-Port Static RAM
Features
■ True dual-ported memory cells which allow simultaneous
access of the same memory location
■ 32 K × 16 organization (CY7C027)
■ 64 K × 16 organization (CY7C028)
■ 0.35 micron CMOS for optimum speed and power
■ High speed access: 15 and 20 ns
■ Low operating power
■ Active: ICC = 180 mA (typical)
■ Standby: ISB3 = 0.05 mA (typical)
■ Fully asynchronous operation
■ Automatic power down
Logic Block Diagram
R/WL
UBL
■ Expandable data bus to 32 bits or more using Master/Slave
chip select when using more than one device
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flags for port-to-port communication
■ Separate upper-byte and lower-byte control
■ Dual chip enables
■ Pin select for Master or Slave
■ Commercial and industrial temperature ranges
■ Available in 100-pin TQFP
■ Pb-free packages available
R/WR
UBR
CE0L
CE1L
LBL
OEL
CEL
I/O8L–I/O15[1L]
I/O0L–I/O[72L]
8
8
I/O
Control
I/O
Control
CER
CE0R
CE1R
LBR
OER
8 I/O8L–I/[O1]15R
8 I/O0L–I/O[2]7R
A0L–A[134]/15L
15/16
Address
Decode
True Dual-Ported
RAM Array
Address
Decode
15/16
A0R–A[134] /15R
A0L–A[134]/15L
CEL
OEL
R/WL
SEML
BUSYL[4]
INTL
UBL
LBL
15/16
Notes
1. I/O8–I/O15 for × 16 devices
2. I/O0–I/O7 for × 16 devices
3. A0–A14 for 32K; A0–A15 for 64K devices.
4. BUSY is an output in master mode and an input in slave mode.
Interrupt
Semaphore
Arbitration
M/S
15/16
A0R–A[134] /15R
CER
OER
R/WR
SEMR
[4] BUSYR
INTR
UBR
LBR
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06042 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 28, 2013
CY7C027
CY7C028
Functional Description
The CY7C027 and CY7C028 are low power CMOS 32 K,
64 K × 16 dual-port static RAMs. Various arbitration schemes
are included on the devices to handle situations when multiple
processors access the same piece of data. Two ports are
provided, permitting independent, asynchronous access for
reads and writes to any location in memory. The devices can be
used as standalone 16-bit dual-port static RAMs or multiple
devices can be combined to function as a 32-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 32-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor and
multiprocessor designs, communications status buffering, and
dual-port video/graphics memory.
Each port has independent control pins: dual chip enables (CE0
and CE1), read or write enable (R/W), and output enable (OE).
Two flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The interrupt flag
(INT) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch (semaphore)
at any time. Control of a semaphore indicates that a shared
resource is in use. An automatic power down feature is controlled
independently on each port by the chip enable pins.
The CY7C027 and CY7C028 are available in 100-pin Thin Quad
Flat pack (TQFP) packages.
Document Number: 38-06042 Rev. *J
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