|
STMicroelectronics |
STM32F205xx
STM32F207xx
ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM,
USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
Preliminary data
Features
■ Core: ARM 32-bit Cortex™-M3 CPU with
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
performance from Flash memory, frequency up
to 120 MHz, memory protection unit,
150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1)
■ Memories
– Up to 1 Mbyte of Flash memory
– Up to 128 + 4 Kbytes of SRAM
– Flexible static memory controller that
supports Compact Flash, SRAM, PSRAM,
NOR and NAND memories
– LCD parallel interface, 8080/6800 modes
■ Clock, reset and supply management
– 1.8 to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– 4 to 26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
■ Low power
– Sleep, Stop and Standby modes
–V BAT supply for RTC, 20 × 32 bit backup
registers, and optional 4 KB backup SRAM
■ 3 × 12-bit, 0.5 µs A/D converters
– up to 24 channels
– up to 6 MSPS in triple interleaved mode
■ 2 × 12-bit D/A converters
■ General-purpose DMA
– 16-stream DMA controller with centralized
FIFOs and burst support
■ Up to 17 timers
– Up to twelve 16-bit and two 32-bit timers,
each with up to 4 IC/OC/PWM or pulse
counter and quadrature (incremental)
encoder input
■ Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™
FBGA
FBGA
LQFP64 (10 × 10 mm)
LQFP100 (14 × 14 mm)
LQFP144 (20 × 20 mm)
LQFP176 (24 × 24 mm)(1)
UFBGA176
WLCSP64+2
(10 × 10 mm) (0.400 mm pitch)
1. Package not in production (for development only).
■ Up to 140 I/O ports with interrupt capability:
– Up to 136 fast I/Os up to 60 MHz
– Up to 138 5 V-tolerant I/Os
■ Up to 15 communication interfaces
– Up to 3 × I2C interfaces (SMBus/PMBus)
– Up to 4 USARTs and 2 UARTs (7.5 Mbit/s,
ISO 7816 interface, LIN, IrDA, modem
control)
– Up to 3 SPIs (30 Mbit/s), 2 with muxed I2S
to achieve audio class accuracy via audio
PLL or external PLL
– 2 × CAN interfaces (2.0B Active)
– SDIO interface
■ Advanced connectivity
– USB 2.0 full-speed device/host/OTG
controller with on-chip PHY
– USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
– 10/100 Ethernet MAC with dedicated DMA:
supports IEEE 1588v2 hardware, MII/RMII
■ 8- to 14-bit parallel camera interface: up to
27 Mbyte/s at 27 MHz or 48 Mbyte/s at 48 MHz
■ CRC calculation unit, 96-bit unique ID
■ Analog true random number generator
Table 1. Device summary
Reference
Part number
STM32F205xx
STM32F207xx
STM32F205RB, STM32F205RC, STM32F205RE,
STM32F205RF, STM32F205RG, STM32F205VB,
STM32F205VC, STM32F205VE, STM32F205VF
STM32F205VG, STM32F205ZC, STM32F205ZE,
STM32F205ZF, STM32F205ZG
STM32F207IC, STM32F207IE, STM32F207IF,
STM32F207IG, STM32F207ZC, STM32F207ZE,
STM32F207ZF, STM32F207ZG, STM32F207VC,
STM32F207VE, STM32F207VF, STM32F207VG
November 2010
Doc ID 15818 Rev 5
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/147
www.st.com
1
http://www.Datasheet4U.com
Contents
Contents
STM32F205xx, STM32F207xx
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 16
2.2.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.3 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 16
2.2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 17
2.2.6 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.7 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.8 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.9 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.10 FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.11 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 19
2.2.12 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.13 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.14 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.15 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.16 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.17 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.18 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . 23
2.2.19 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.20 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.21 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.22 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2.23 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2.24 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2.25 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2.26 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2.27 Universal synchronous/asynchronous receiver transmitters
(UARTs/USARTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2.28 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/147
Doc ID 15818 Rev 5
|