NT5SV8M16FS 반도체 회로 부품 판매점
128Mb Synchronous DRAM
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 NANYA |
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
Features
• High Performance:
Maximum Operating Speed
CAS
Latency
PC166
PC133
(6K/6KI) (75B/75BI)
2 7.5 10 ns
3 6 7.5 ns
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• Four Banks controlled by BA0/BA1 (Bank Select)
• Programmable CAS Latency: 2, 3
• Programmable Burst Length: 1, 2, 4, 8 or full page
• Programmable Wrap: Sequential or Interleave
• Multiple Burst Read with Single Write Option
• Automatic and Controlled Precharge Command
• Dual Data Mask for byte control (x16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• Standard Power operation
• Random Column Address every CK (1-N Rule)
• Single Power Supply, either 3.3V
• LVTTL compatible
• Packages: TSOP-Type II
• Lead-free & Halogen-free product available
Description
The NT5SV8M16FS, and NT5SV8M16FT are four-bank Syn-
chronous DRAMs organized as 2Mbit x 16 I/O x 4 Bank.
These synchronous devices achieve high-speed data trans-
fer rates of up to 166MHz by employing a pipeline chip archi-
tecture that synchronizes the output data to a system clock.
The device is designed to comply with all JEDEC standards
set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, and data input/out-
put (I/O or DQ) circuits are synchronized with the positive
edge of an externally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which are exam-
ined at the positive edge of each externally applied clock
(CK). Internal chip operating modes are defined by combina-
tions of these signals and a command decoder initiates the
necessary timings for each operation. A fifteen bit address
bus accepts address data in the conventional RAS/CAS mul-
tiplexing style. Twelve addresses (A0-A11) and two bank
select addresses (BA0, BA1) are strobed with RAS. Nine col-
umn addresses (A0-A8) plus bank select addresses and A10
are strobed with CAS.
Prior to any access operation, the CAS latency, burst length,
and burst sequence must be programmed into the device by
address inputs A0-A11, BA0, BA1 during a mode register set
cycle. In addition, it is possible to program a multiple burst
sequence with single write cycle for write through cache
operation.
Operating the four memory banks in an interleave fashion
allows random access operation to occur at a higher rate
than is possible with standard DRAMs. A sequential and gap-
less data rate of up to 166MHz is possible depending on
burst length, CAS latency, and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are sup-
ported.
REV 1.3
9/2008
1
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Free Datasheet http://www.datasheet4u.net/
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
Ordering Information
Organization
Part Number
NT5SV8M16FS-6K
NT5SV8M16FS-6KI
NT5SV8M16FS-75B
8M x 16
NT5SV8M16FS-75BI
NT5SV8M16FT-6K
NT5SV8M16FT-6KI
NT5SV8M16FT-75B
NT5SV8M16FT-75BI
CL = CAS Latency
Lead-free products are also halogen-free
Nanya Technology Corporation
Hwa Ya Technology Park 669
Fu Hsing 3rd Rd., Kueishan,
Taoyuan, 333, Taiwan, R.O.C.
Tel: +886-3-328-1688
Package
400mil 54-PIN
TSOP II
Lead-Free
400mil 54-PIN
TSOP II
Power
3.3V
Speed Grade
Clock Frequency
CL-tRCD-tRP
Notes
166MHz-3-3-3
Lead free packaging
Lead free packaging
133MHz-3-3-3
Lead free packaging
Lead free packaging
166MHz-3-3-3
133MHz-3-3-3
Please visit our home page for more information: www.nanya.com
REV 1.3
9/2008
2
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Free Datasheet http://www.datasheet4u.net/
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