LC4064C-25TN100C 반도체 회로 부품 판매점
Super Fast High Density PLDs
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 Lattice Semiconductor |
ispMACHTM 4000V/B/C/Z Family
3.3V/2.5V/1.8V In-System Programmable
January 2004
Coolest Power
SuperFASTTM High Density PLDs
Data Sheet
Features
C
TM
■ Broad Device Offering
• Multiple temperature range support
■ High Performance
• fMAX = 400MHz maximum operating frequency
• tPD = 2.5ns propagation delay
• Up to four global clock pins with programmable
– Commercial: 0 to 90°C junction (Tj)
– Industrial: -40 to 105°C junction (Tj)
– Automotive: -40 to 130°C junction (Tj)
clock polarity control
■ Easy System Integration
• Up to 80 PTs per output
• Superior solution for power sensitive consumer
applications
■ Ease of Design
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
• Enhanced macrocells with individual clock,
• Operation with 3.3V (4000V), 2.5V (4000B) or
reset, preset and clock enable controls
1.8V (4000C/Z) supplies
• Up to four global OE controls
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
• Individual local OE control per I/O pin
• Excellent First-Time-FitTM and refit
• Fast path, SpeedLockingTM Path, and wide-PT
interfaces
• Hot-socketing
• Open-drain capability
path • Input pull-up, pull-down or bus-keeper
• Wide input gating (36 input logic blocks) for fast
• Programmable output slew rate
counters, state machines and address decoders
• 3.3V PCI compatible
■ Zero Power (ispMACH 4000Z) and Low
• IEEE 1149.1 boundary scan testable
Power (ispMACH 4000V/B/C)
• 3.3V/2.5V/1.8V In-System Programmable
• Typical static current 10µA (4032Z)
(ISP™) using IEEE 1532 compliant interface
• Typical static current 1.3mA (4000C)
• I/O pins with fast setup path
• 1.8V core low dynamic power
• Lead-free package options
• ispMACH 4000Z operational down to 1.6V VCC
Table 1. ispMACH 4000V/B/C Family Selection Guide
Macrocells
I/O + Dedicated
Inputs
tPD (ns)
tS (ns)
tCO (ns)
fMAX (MHz)
Supply Voltages (V)
Pins/Package
ispMACH
4032V/B/C
32
30+2/32+4
2.5
1.8
2.2
400
3.3/2.5/1.8V
44 TQFP
48 TQFP
ispMACH
4064V/B/C
64
30+2/32+4/
64+10
2.5
1.8
2.2
400
3.3/2.5/1.8V
44 TQFP
48 TQFP
100 TQFP
ispMACH
4128V/B/C
128
64+10/92+4/
96+4
2.7
1.8
2.7
333
3.3/2.5/1.8V
100 TQFP
128 TQFP
144 TQFP1
1. 3.3V (4000V) only.
2. 128-I/O and 160-I/O configurations.
ispMACH
4256V/B/C
256
64+10/96+14/
128+4/160+4
3.0
2.0
2.7
322
3.3/2.5/1.8V
100 TQFP
144 TQFP1
176 TQFP
256 fpBGA2
ispMACH
4384V/B/C
384
128+4/192+4
ispMACH
4512V/B/C
512
128+4/208+4
3.5
2.0
2.7
322
3.3/2.5/1.8V
3.5
2.0
2.7
322
3.3/2.5/1.8V
176 TQFP
256 fpBGA
176 TQFP
256 fpBGA
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
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ispm4k_20z
Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
Table 2. ispMACH 4000Z Family Selection Guide
Macrocells
I/O + Dedicated Inputs
tPD (ns)
tS (ns)
tCO (ns)
fMAX (MHz)
Supply Voltage (V)
Max. Standby Icc (µA)
Pins/Package
ispMACH 4032ZC
32
32+4/32+4
3.5
2.2
3.0
267
1.8
20
48 TQFP
56 csBGA
ispMACH 4064ZC
64
32+4/32+12/
64+10/64+10
3.7
2.5
3.2
250
1.8
25
48 TQFP
56 csBGA
100 TQFP
132 csBGA
ispMACH 4128ZC
128
64+10/96+4
4.2
2.7
3.5
220
1.8
35
100 TQFP
132csBGA
ispMACH 4256ZC
256
64+10/96+6/
128+4
4.5
2.9
3.8
200
1.8
55
100 TQFP
132 csBGA
176 TQFP
ispMACH 4000 Introduction
The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend
of Lattice’s two most popular architectures: the ispLSI® 2000 and ispMACH 4A. Retaining the best of both families,
the ispMACH 4000 architecture focuses on significant innovations to combine the highest performance with low
power in a flexible CPLD family.
The ispMACH 4000 combines high speed and low power with the flexibility needed for ease of design. With its
robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil-
ity, routing, pin-out retention and density migration.
The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O com-
binations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA) and Fine Pitch BGA (fpBGA) packages ranging
from 44 to 256 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key parameters.
The ispMACH 4000 family has enhanced system integration capabilities. It supports 3.3V (4000V), 2.5V (4000B)
and 1.8V (4000C/Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely
driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The ispMACH
4000 also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up
resistors, pull-down resistors, open drain outputs and hot socketing. The ispMACH 4000 family members are 3.3V/
2.5V/1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary
scan testing capability also allows product testing on automated test equipment.
Overview
The ispMACH 4000 devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected
by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which
contain multiple I/O cells. This architecture is shown in Figure 1.
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