파트넘버.co.kr ALM-12124 데이터시트 PDF


ALM-12124 반도체 회로 부품 판매점

High Power SPDT Switch



AVAGO 로고
AVAGO
ALM-12124 데이터시트, 핀배열, 회로
ALM-12124
1.88 GHz – 2.025 GHz
50 Watt High Power SPDT Switch with LNA Module
Data Sheet
Description
Avago Technologies’ALM-12124 is a multi-chip integrated
module that comprise of a 50 Watt CW high power SPDT
switch, 1st stage low noise amplifier and 2nd stage high
gain driver amplifier through the use of Avago Techno-
logies’ proprietary 0.25 m GaAs Enhancement-mode
pHEMT process and low distortion silicon PIN diode
technologies.
The ALM-12124 is housed in a compact 8.0 x 8.0 x 1.2 mm3
molded-chips-on-board (MCOB) module package with 24
pin configuration pads, offering significant PCB space saving
as compare to conventional discrete design approach.
The device offers high power protection switch (Tx mode
operation) with very low insertion loss. During Rx mode
operation, the receiver chain provides a very low NF and
high gain that makes it an ideal choice for cellular infra-
structure in TD-SCDMA and TD-LTE applications.
Component Image
Package Size : 8.0 x 8.0 x 1.2 mm3
AVAGO
12124
WWYY
XXXX
Gnd
Gnd
Gnd
Gnd
Gnd
Rx Out
Gnd
Vbias Vc 1 Gnd Gnd Gnd Tx
Pin 1
Ant
Gnd
Gnd
Vc 2
Vg
Vdd1
TOP VIEW
LNA2 Gnd Gnd Gnd Gnd LNA1
_In _Out
BOTTOM VIEW
Note:
Package marking provides orientation and identification
“12124” = Device Part Number
“WWYY” = Work week and year of manufacture
“XXXX” = Last 4 digit of lot number
Notes:
1. Enhancement mode technology employs positive Vgs, thereby elimi-
nating the need of negative gate voltage associated with conven-
tional depletion mode devices.
Features
 Very Low Noise Figure
 High Power Switch design
 50 dB isolation between LNA1_Out and LNA2_In
 Small package size 8.0 x 8.0 x 1.2 mm3
 GaAs E-pHEMT Technology [1]
 Low Distortion Silicon PIN Diode Technology
 MSL 2a and Lead-free
Specifications
Typical Performance at 1.90 GHz (Rx mode)
 39.5 dB Gain
 0.80 dB Noise Figure
 36.4 dBm Output IP3
Typical Performance at 1.90 GHz (Tx mode)
 0.27 dB insertion loss
 40 dB Ant to LNA1 Isolation
Applications
 High power switch LNA module for TD-SCDMA and
TD-LTE base station front-end RF application.
Block Diagram with Simplified Schematic
Vc1 Vbias Vdd2
External
50 ohm
termination
Tx
C2
C6
C10
C7
Ant C1
Vc2
PA Vg
R1
C9
Vdd1 C3
Switch bias
circuitry
C8
L1
C5
Rx Out
C4
LNA1_Out LNA2_In
Free Datasheet http://www.datasheet4u.com/


ALM-12124 데이터시트, 핀배열, 회로
Absolute Maximum Rating [1] TA = 25° C
Symbol
Vc1,max
Ic1 ,max
Vc2,max
Ic2,max
Vbias
Vdd1,2
Vg
Pin,max
Pin,max
Pin,max
Rx Pdiss
Tx Pdiss
Tj
TSTG
Tamb
Parameter
Device Control Voltage 1
(At Rx mode)
Device Control Current 1
(At Rx mode)
Device Control Voltage 2
(At Tx mode)
Device Control Current 1
(At Tx mode)
Device Bias Voltage
Device Voltage, RF output to ground
Gate Voltage
Ant CW RF Input Power (Tx mode);
5 mins testing
Ant CW RF Input Power (Rx mode)
(Vdd = 5.0 V, Idd1 = 50 mA)
LNA2_In CW RF Input Power
(Vdd = 5.0 V, Idd2 = 120 mA)
Rx mode Total Power Dissipation [3]
LNA1
Rx mode Total Power Dissipation [3]
LNA2
Tx mode Total Power Dissipation
Junction Temperature
Storage Temperature
Ambient Temperature
Units Absolute Max.
V 30
mA 57
V 30
mA 57
V 5.5
V 5.5
V 0.7
dBm +47.5
dBm +20
dBm +25
W 0.3
W 0.5
W 8.70
°C 150
°C -65 to 150
°C -40 to 85
Rx mode Thermal Resistance [2]
LNA1: Vdd1 = 5.0 V, Idd1 = 50 mA
LNA2: Vdd2 = 5.0 V, Idd2 = 120 mA;
LNA1 jc = 72.4°C/W
LNA2 jc = 65.0°C/W
Tx mode Thermal Resistance [2]
LNA1: Vdd1 = 5.0 V, Idd1 = 50 mA
LNA2: Vdd2 = 5.0 V, Idd2 = 120 mA;
jc = 11.7°C/W
Notes:
1. Operation of this device in excess of any of
these limits may cause permanent damage.
2. Thermal resistance measured using Infra-Red
Measurement Technique.
3. Power dissipation in Rx mode with both LNA1
and LNA2 turned on. Board temperature TB is
25° C.
LNA1: Derate at 14 mW/°C for TB > 114° C.
LNA2: Derate at 15.6 mW/°C for TB > 92° C.
4. Switch Turn On Condition:
Tx mode: Vbias = 5 V, Vc1 = 0 V, Vc2 = 28 V
Rx mode: Vbias = 5 V, Vc1 = 28 V, Vc2 = 0 V
Rx/Tx Switch Operating Truth Table [1]
Mode
Vbias (V)
Vc1 (V)
Vc2 (V)
Rx (Ant – Rx)
5
28 0
Tx (Ant – Tx)
5
0
28
Note:
1. Any state other than described above in the truth table may cause permanent damage to
the device.
2
Free Datasheet http://www.datasheet4u.com/




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High Power SPDT Switch - AVAGO