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INTEGRATED CIRCUITS
AN124
External synchronization for the
NE5561/5568
1988 Dec
Philips
Semiconductors
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr
Philips Semiconductors
External synchronization for the NE5561/5568
Application note
AN124
Synchronization of the 5561 can be accomplished by forcing the
timing pin (Pin 5) above the 5.6V sawtooth limit comparator for a
short time.
É+5.6V
ÉÉÉÉ+1.1V
TIMING
SAWTOOTH
+1V (TYP)
EXTERNAL
SYNC
SL00788
Figure 1.
This can be accomplished with a simple diode-coupled narrow pulse
source with fairly low source impedance:
2 8.4V
NE5561/
5568
5
IN914
100pF
RT
CT
SYNC
1V
0
A drawback to this approach is that when the 5.6V threshold is
reached, a discharge transistor is turned on to quickly pull the timing
capacitor to ground and will also attempt to pull the pulse generator
to ground. This condition can be avoided by keeping the pulse width
very narrow (0.1µs) or by placing a differentiator network between
the pulse generator and the diode.
The differentiator will now produce a positive-going spike with the
positive edge of the sync pulse, resetting the sawtooth without
passing too much current through the discharge transistor. The
negative spike produced by the falling edge of the clock will be
blocked by the diode and will have no effect on the sawtooth ramp.
A narrow sync pulse is no longer necessary while a sharp-edged
pulse is. The value of CD should be sufficient to ensure that a 10V
pulse will drive the capacitor, CT, high enough to trip the 5.6V
comparator according to:
CT∆VCT=CD(∆VCT-VD)
This relates the magnitude of the spike to the size of the pulse. Also
assume RDCD<1µs.
The free-running frequency of the slaved 5561 should be slightly
lower than the sync frequency for proper operation.
Figure 2.
SL00789
1988 Dec
2
Datasheet pdf - http://www.DataSheet4U.net/
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