CY25561 반도체 회로 부품 판매점
Spread Spectrum Clock Generator
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 Cypress Semiconductor |
CY25561
Spread Spectrum Clock Generator
Features
■ 50 to 166 MHz Operating Frequency Range
■ Wide Range of Spread Selections:9
■ Accepts Clock and Crystal Inputs
■ Low Power Dissipation
❐ 70 mW–Typ at 66 MHz
■ Frequency Spread Disable Function
■ Center Spread Modulation
■ Low Cycle-to-cycle Jitter
■ 8-pin SOIC Package
Logic Block Diagram
Xin/
CLK
1
300 K
Xout 8
Applications
■ Desktop, notebook, and tablet PCs
■ VGA controllers
■ LCD panels and monitors
■ Workstations and servers
Benefits
■ Peak EMI reduction by 8 to16 dB
■ Fast time to market
■ Cost reduction
REFERENCE
DIVIDER
MODULATION
CONTROL
PD CP
FEEDBACK
DIVIDER
Loop
Filter
vco
VDD 2
VSS 3
INPUT
DECODER
LOGIC
VDD
20K
VDD
20K
5
SSCC
20K
VSS
67
S1 S0
20K
VSS
DIVIDER
&
MUX
4 SSCLK
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4NUu.nmebt er: 38-07242 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 15, 2008
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CY25561
Pinout
Figure 1. Pin Configuration
XIN/CLK 1
VDD 2
VSS 3
SSCLK 4
CY25561
8 XOUT
7 S0
6 S1
5 SSCC
Table 1. Pin Description
Pin Name
1 Xin/CLK
2 VDD
3 GND
4 SSCLK
5 SSCC
6 S1
7 S0
8 Xout
Type
I
P
P
O
I
I
I
O
Description
Clock or crystal connection input. Refer to Table 2 for input frequency range selection.
Positive power supply
Power supply ground
Modulated clock output
Spread spectrum clock control (enable/disable) function. SSCG function is enabled when input
is high and disabled when input is low. This pin is pulled high internally.
Tri-level logic input control pin used to select frequency and bandwidth. Frequency/Bandwidth
selection and tri-level logic programming. See Figure 2. Pin 6 has internal resistor divider
network to VDD and VSS. Refer to Logic Block Diagram on page 1.
Tri-level logic input control pin used to select frequency and bandwidth. Frequency/Bandwidth
selection and tri-level logic programming. See Figure 2. Pin 7 has internal resistor divider
network to VDD and VSS. Refer to Logic Block Diagram on page 1.
Oscillator output pin connected to crystal. Leave this pin unconnected If an external clock drives
Xin/CLK.
General Description
CY25561 is a spread spectrum clock generator (SSCG) IC used
to reduce electromagnetic Interference (EMI) found in today’s
high speed digital electronic systems.
CY25561 uses a Cypress proprietary Phase Locked Loop (PLL)
and Spread Spectrum Clock (SSC) technology to synthesize and
frequency modulate the input frequency of the reference clock.
By doing this, the measured EMI at the fundamental and
harmonic frequencies of clock (SSCLK) is reduced.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory requirements and time to
market without degrading the system performance.
CY25561 is a very simple and versatile device to use. The
frequency and spread percentage range is selected by
programming S0 and S1 digital inputs. These inputs use three
logic states including high (H), low (L), and middle (M) logic
levels to select one of the nine available spread percentage
ranges. Refer to Table 2 for programming details.
CY25561 is intended for use with applications with a reference
frequency in the range of 50 to 166 MHz.
A wide range of digitally selectable spread percentages is made
possible by using tri-level (high, low, and middle) logic at the S0
and S1 digital control inputs.
The output spread (frequency modulation) is symmetrically
centered on the input frequency.
Spread spectrum clock control (SSCC) function enables or
disables the frequency spread and is provided for easy
comparison of system performance during EMI testing.
CY25561 is available in an eight-pin SOIC package with a 0°C
to 70°C operating temperature range.
Note: Refer to the CY25560 data sheet for operation at frequencies from 25 to100 MHz.
Document Number: 38-07242 Rev. *C
Page 2 of 9
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국내 전력반도체 판매점
상호 : 아이지 인터내셔날
전화번호 : 051-319-2877
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전력반도체 문의 : 010-3582-2743
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