RX62N 반도체 회로 부품 판매점
(RX62N / RX621) 100 MHz 32-bit RX MCU
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 Renesas Technology |
Features
Datasheet
RX62N/RX621 Group
RENESAS 32-Bit MCU
R01DS0052EJ0110
Rev.1.10
100 MHz 32-bit RX MCU with FPU, 165 DMIPS, up to 512-Kbyte Flash, Feb 10, 2011
Ethernet, USB 2.0 Full-Speed Host/Function/OTG, CAN, 12-bit ADC, TFT-LCD,
RTC, up to 14 communication channels
Features
■32-bit RX CPU Core
Delivers 165 DMIPS at a maximum operating frequency of
100 MHz
Single Precision 32-bit IEEE-754 Floating Point
Accumulator: 32 × 32 to 64-bit result, one instruction
Mult/Divide Unit, 32 × 32 Multiply in one CPU clock for
multiple instructions
Interrupt response in as few as 5 CPU clock cycles
CISC-Harvard Architecture with 5-stage pipeline
Variable length instructions, ultra compact code
Supports the Memory Protection Unit (MPU)
Background JTAG debug plus high-speed trace
■Low Power Design and Architecture
2.7V to 3.6V operation from a single supply
480 µA/MHz Run Mode with all peripherals on
Deep Software Standby Mode with RTC
Four low power modes
■Main Flash Memory, no Wait-State
100 MHz operation, 10 nsec read cycle
No wait states for read at full CPU speed
256K, 384K, 512K Byte size options
For Instructions or Operands
Programming from USB, SCI, JTAG, user code
■Data Flash Memory
Up to 32K Bytes with 30K Erase Cycles
Background Erase/Program does not stall CPU
■SRAM, no Wait-State
64K or 96K Byte size options
For Operands or Instructions
Back-up retention in Deep Software Standby Mode
■DMA
Four fully programmable internal DMA channels
Two EXDMA channels for external-to-external transfers
Data Transfer Controller (DTC)
■Reset and Supply Management
Power-On Reset (POR) monitor/generator
Low Voltage Detect (LVD) with precision setting
■System Clocking with Clock Monitoring
External crystal, 8 MHz to 14 MHz to Internal PLL
PLL source to system, USB, and Ethernet
Internal 125 kHz LOCO for IWDT
External crystal, 32 kHz for RTC
■Real Time Clock
Full calendar function, BCD format
■Two Independent Watchdog Timers
125-kHz LOCO operation
R01DS0052EJ0110 Rev.1.10
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TFLGA85 7×7mm, 0.65mm pitch
TFLGA145 9×9mm, 0.65mm pitch
LFBGA176 13×13mm, 0.8mm pitch
LQFP100 14×14mm, 0.5mm pitch
LQFP144 20×20mm, 0.5mm pitch
■Up to 14 Communication Interfaces
(2) USB 2.0 Full-Speed interfaces with PHY
Supports Host/Function/OTG
10 endpoints for types: Control, Interrupt, Bulk, Isochronous
(1) Ethernet MAC 10/100 Mbps, Half or Full Duplex
Supported.
Dedicated DMA with 2-Kbyte transmit and receive FIFOs.
RMII or MII interface to external PHY
(1) CAN ISO11898-1, supports 32 mailboxes
(6) SCI channels: Asynchronous, clock sync, smartcard,
and 9-bit modes
(2) I2C interfaces up to 1M bps, SMBus support
(2) RSPI
■External Address Space
Eight CS areas (8 × 16 Mbytes)
128-Mbyte SDRAM area
8-/16-/32-bit bus space selectable for each area
■TFT-LCD up to WQVGA resolution
■Up to 20 Extended Function Timers
(12) 16-bit MTU2
Input capture, Output Compare, PWM output, phase count
mode
(4) 8-bit TMR
(4) 16-bit CMT
■1-MHz ADC units with two combination choices
12-bit × 8 ch. unit with single sample/hold circuit
or (2) 10-bit × 4 ch units each with a sample/hold circuit
AD-converted value addition mode (12-bit A/D converter)
■10-bit DAC, 2 channels
■Up to 128 GPIO
5V tolerant, Open-Drain, Internal Pull-up
■Operation Temp
–40°C to +85°C
Page 1 of 146
RX62N Group, RX621 Group
1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 lists the functions of products.
Table 1.1 Outline of Specifications (1 / 4)
Classification
CPU
Module/Function
CPU
Memory
FPU
ROM
RAM
Data flash
MCU operating modes
Clock
Clock generation
circuit
Reset
Voltage detection circuit
Low power
consumption
Low power
consumption
facilities
Description
· Maximum operating frequency: 100 MHz
· 32-bit RX CPU
· Minimum instruction execution time: One instruction per state (cycle of the system clock)
· Address space: 4-Gbyte linear
· Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Nine 32-bit registers
Accumulator: One 64-bit register
· Basic instructions: 73
· Floating-point instructions: 8
· DSP instructions: 9
· Addressing modes: 10
· Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
· On-chip 32-bit multiplier: 32 x 32 64 bits
· On-chip divider: 32 / 32 32 bits
· Barrel shifter: 32 bits
· Memory-protection unit (MPU) (as an optional function)*1
· Single precision (32-bit) floating point
· Data types and floating-point exceptions in conformance with the IEEE754 standard
· ROM capacity: 512 Kbytes (max.)
· Two on-board programming modes
Boot mode (The user MAT is programmable via the SCI and USB.)
User program mode
· Parallel programmer mode (for off-board programming)
RAM capacity: 96 Kbytes (max.)
Data flash capacity: 32 Kbytes
· Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled
expansion mode (software switching)
· Two circuits: Main clock oscillator and subclock oscillator
· Internal oscillator: Low-speed on-chip oscillator
· Structure of a PLL frequency synthesizer and frequency divider for selectable operating
frequency
· Oscillation stoppage detection
· Independent frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clock (PCLK), and external bus clock (BCLK)
The CPU and other bus masters run in synchronization with the system
clock (ICLK): 8 to 100 MHz
Peripheral modules run in synchronization with the peripheral module
clock (PCLK): 8 to 50 MHz
· Devices connected to the external bus run in synchronization with the external bus
clock (BCLK): 8 to 50 MHz
· Pin reset, power-on reset, voltage-monitoring reset, watchdog timer reset, independent
watchdog timer reset, and deep software standby reset
· When the voltage on VCC falls below the voltage detection level (Vdet), an internal reset
or internal interrupt is generated.
· Module stop function
· Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
R01DS0052EJ0110 Rev.1.10
Feb 10, 2011
Page 2 of 146
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