CY26580 반도체 회로 부품 판매점
Network Applications Clock
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 Cypress Semiconductor |
Features
• Integrated phase-locked loop (PLL)
• Low-jitter, high-accuracy outputs
• 3.3V operation
CY26580
PacketClock™
Network Applications Clock
Benefits
• Internal PLL with precision operation
• Meets critical timing requirements in complex system
designs
• Enables application compatibility
Frequency Table
Part Number Outputs
CY26580-1
2
Input Frequency
125MHz or 25-MHz driven
Output Frequencies
100 MHz, 133.33 MHz
Logic Block Diagram
CLK
OSC.
QΦ
VCO
P
PLL
OUTPUT
MULTIPLEXER
AND
DIVIDERS
133.33 MHz
100 MHz
SEL_25
SEL_CLK
Pin Configuration
CY26580
20-pin SSOP (QSOP)
NC
NC
CLK
VDD
NC
GND
NC
NC
NC
133 MHz
1
2
3
4
5
6
7
8
9
10
20 NC
19 SEL_CLK
18 NC
17 100 MHz
16 VDD
15 NC
14 GND
13 NC
12 NC
11 SEL_25
VDD VDD GND GND
Input Select Options
SEL_25
SEL_CLK
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01
11
Input Type
Driven
Driven
Input Frequency
CLK1
Do not use
125 133.33
25 133.33
CLK2
100
100
Unit
MHz
MHz
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07536 Rev. *B
Revised June 03, 2004
CY26580
Pin Description
Pin Name
NC
NC
CLK
VDD
NC
GND
NC
NC
NC
133 MHz
SEL_25
NC
NC
GND
NC
VDD
100 MHz
NC
SEL_CLK
NC
Pin Number
Pin Description
1 No Connect
2 No Connect
3 Reference Input
4 Voltage Supply
5 No Connect
6 Ground
7 No Connect
8 No Connect
9 No Connect
10 133.33-MHz Clock Output
11 Reference Frequency Select Input; 0 = 125 MHz, 1 = 25 MHz, weak internal pull-up
12 No Connect
13 No Connect
14 Ground
15 No Connect
16 Voltage Supply
17 100-MHz Clock Output
18 No Connect
19 Reference Select Input; Set to 1 = Driven, weak internal pull-up
20 No Connect
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Document #: 38-07536 Rev. *B
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CY26580 data
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국내 전력반도체 판매점
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