CY62136ESL 반도체 회로 부품 판매점
2 Mbit (128K x 16) Static RAM
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 Cypress Semiconductor |
CY62136ESL MoBL®
2 Mbit (128K x 16) Static RAM
Features
■ Very high speed: 45 ns
■ Wide voltage range: 2.2V to 3.6V and 4.5V to 5.5V
■ Ultra low standby power
❐ Typical standby current: 1 μA
❐ Maximum standby current: 7 μA
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Available in Pb-free 44-pin TSOP II package
Functional Description
The CY62136ESL is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
when addresses are not toggling. Placing the device into standby
.
Logic Block Diagram
mode reduces power consumption by more than 99% when
deselected (CE HIGH). The input and output pins (IO0 through
IO15) are placed in a high impedance state when:
■ Deselected (CE HIGH)
■ Outputs are disabled (OE HIGH)
■ Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■ Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7) is written into the location
specified on the address pins (A0 through A16). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15)
is written into the location specified on the address pins (A0
through A16).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the “Truth Table” on page 10 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
DATA IN DRIVERS
AA190
A8
A7
A6
A5 128K x 16
A4 RAM Array
A3
A2
AA01
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-48147 Rev. *A
www.DataSheet.in
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 15, 2009
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CY62136ESL MoBL®
Pin Configuration
Figure 1. 44-Pin TSOP II (Top View) [1]
A4
A3
A2
A1
A0
CE
IO0
IO1
IO2
IO3
VCC
VSS
IO4
IO5
IO6
IO7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 A5
43 A6
42 A7
41 OE
40 BHE
39 BLE
38 IO15
37 IO14
36 IO13
35 IO12
34 VSS
33 VCC
32 IO11
31 IO10
30 IO9
29 IO8
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
Product Portfolio
Product
Range
VCC Range (V) [2]
CY62136ESL Industrial 2.2V to 3.6V and 4.5V to 5.5V
Speed
(ns)
45
Power Dissipation
Operating ICC, (mA)
f = 1MHz
Typ [3] Max
f = fmax
Typ [3] Max
Standby,
(μA)
ISB2
Typ [3] Max
2 2.5 15 20 1
7
Notes
1. NC pins are not connected on the die.
2. Datasheet specifications are not guaranteed for VCC in the range of 3.6V to 4.5V.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3V, and VCC = 5V, TA = 25°C.
Document #: 001-48147 Rev. *A
Page 2 of 12
www.DataSheet.in
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