ARM1156T2-S 반도체 회로 부품 판매점
TCM-only Processor
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 LSI Logic |
ARM1156T2-S TCM-only Processor
with ECC Protection and Reference Design CW001145
www.DataSheet4U.com
OVERVIEW
The LSI Logic implementation of the ARM1156T2-S processor for cell-based
ASIC provides an integration friendly solution for applications like mass storage
devices that require the deterministic performance of Tightly Coupled Memories
(TCM). This implementation of the ARM1156T2-S processor is a timing-closed
hardmac that runs at 450 MHz and provides a higher-performance option to
the ARM966E-S processor with minimal increase in cost. As a member of the
CoreWare® IP library this core will integrate seamlessly with the ASIC design
flow and will help ensure a right-first-time SOC design. LSI Logic’s ARM1156T2-S
hardmac is already timing closed at 450 MHz, thereby eliminating the effort
and risk of closing processor timing at the ASIC level. The processor supports
the ARMv6T2 architecture, including the new Thumb-2 instruction set which
provides the performance of the ARM instructions with the code compression
of the Thumb instructions. The processor core also conforms to the new
AMBA™ 3.0 AXI bus specification for high-performance systems requiring
high data throughput.
I TCM
with ECC
Debug
Interface
VIC Port
Coprocessor
Controller
TCRAM I/F Core TCRAM I/F
VFP
Memory Protection
Instruction
Interface
Data
Interface
Peripheral
Port
64-bit AXI
64-bit AXI
32-bit AXI
Figure 1. ARM1156T2-S processor block diagram
D TCM
with ECC
FEATURES
• 450 MHz timing-closed hardmac
• LSI Logic G90 0.90 nm 1.0 V
process technology
• Configurable TCMs with 64-bit ECC
• AXI bus interface
• Thumb2 instruction support
• Memory Protection Unit (MPU)
• Reference Design
- SRAM/Flash Controller, AXI to AHB
Bridge, AHB to APB Bridge, ECC
protection and logging, Configurable
AXI Interconnect, SSI/SPI, I2C, Interrupt
Controller, UART, Timers, GPIO
BENEFITS
• 450 MHz performance provides
new high-level of performance for
deterministic applications
• Timing closed hardmac reduces timing
closure risk and turn-around time
• 64-bit ECC on TCMs provides soft
error rate protection required by mass
storage and similar applications
without increasing cost or sacrificing
performance
• Thumb2 instructions provide the
performance of ARM with the density
of Thumb reducing the memory
requirements without sacrificing
performance
• Next generation AXI bus enables
better bus performance
• Reference Design with proven
components provides silicon-proven
jump start on subsystem design
• Expert ARM support to help with
architecture, functionality and
integration
ARM1156T2-S TCM-only Processor
with ECC Protection and Reference Design CW001145
www.DataSheet4U.com
Complementing the ARM1156T2-S core is a complete reference design
with all the peripherals needed for an embedded design, including LSI
Logic’s unique ECC Memory Protection core that provides high-performance
and cost-effective soft-error protection for tightly coupled memories on ARM
processors. The reference design includes an Interrupt Controller, Synchronous
Serial Interface, UART, GPIO, I2C, Timers, EBIU, APB bridge and the ECC
Memory Protection Core. Delivered in RTL, the reference design provides a
streamlined methodology for designers to quickly create and verify a custom
processor subsystem for integration into a SoC.
In addition to the ARM1156T2-S processor, customers need additional
IP to provide the connectivity required by their application. To address this
need, LSI Logic provides a complete library of CoreWare® IP from which
customers can quickly create a complete SOC solution. The CoreWare® IP
library provides the industry’s most comprehensive set of IP solutions that are
of proven quality and are designed to work seamlessly with the cell-based
ASIC and RapidChip™ Platform ASIC design flows. CoreWare® IP includes
GigaBlaze® and HyperPHY™ high-speed standards-compliant SerDes, high-
performance ARM and MIPS processors and associated systems and refer-
ence designs, licensable ZSP® DSP cores, processor peripherals and AMBA
on-chip-bus structures, USB cores, Memory PHYs and Controllers, Ethernet
MAC and PHY cores, PCI Express, XGXS, SPI4.2 and other protocol layer IP.
Customers can leverage CoreWare® IP solutions to significantly reduce risk
and turn-around times with complex SoC designs. Additionally, a dedicated
worldwide IP support organization is available to assist customers in all
aspects of CoreWare® SOC design.
Interconnect Matrix
ID
TCM TCM
AXI Slave
Periph
AXI 32
ARM
1156
I-AXI AXI
Fabric
(PL300)
Bridge and
Down
Converter
DRW
AXI-64
Bridge and
Down
Converter
Debug
JTAG Access Port
(DAP)
SRAM/Flash
Controller
Peripheral System
APB BUS
APB BUS
PL022
APB Bridge
12C
APB BUS
ApIntCtii
ApUart ApTimers ApGpio
Remap
Figure 2. Reference Design for ARM1156T2-S processor block diagram
For more information please call:
LSI Logic Corporation
Headquarters
1621 Barber Lane
Milpitas, CA 95035
Tel: 866.574.5741
(within U.S. and Canada)
1.408.954.3108
(outside U.S. and Canada)
Technical Support: 800.633.4545
Corporate Website
www.lsilogic.com
Sales Office Locations
www.lsilogic.com/contacts
LSI Logic, the LSI Logic logo design, RapidChip, the
RapidChip logo, CoreWare, and ZSP are trademarks or
registered trademarks of LSI Logic Corporation. ARM is a
registered trademark of ARM Limited. AMBA is a trademark
of ARM Limited. All other brand and product names may
be trademarks of their respective companies.
LSI Logic Corporation reserves the right to make changes
to any products and services herein at any time without
notice. LSI Logic does not assume any responsibility or lia-
bility arising out of the application or use of any product
or service described herein, except as expressly agreed to
in writing by LSI Logic; nor does the purchase, lease, or
use of a product or service from LSI Logic convey a
license under any patent rights, copyrights, trademark
rights, or any other of the intellectual property rights of
LSI Logic or of third parties.
Copyright ©2005 by LSI Logic Corporation.
All rights reserved.
Order No. C20069
0305.DH - Printed in USA]
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