M1A3P1000 반도체 회로 부품 판매점
ProASIC3 Flash Family FPGAs
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 Actel Corporation |
ProASIC3 Flash Family FPGAs
with Optional Soft ARM® Support
www.DataSheet4U.cvom1.0
®
Features and Benefits
High Capacity
• 15 k to 1 M System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI†
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except ARM-enabled ProASIC®3
devices) via JTAG (IEEE 1532–compliant)†
• FlashLock® to Secure FPGA Contents
Low Power
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS
2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os‡
• Programmable Output Slew Rate† and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL†
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay
Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory†
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
• True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
• M1 and M7 ProASIC3 Devices—Cortex-M1 and CoreMP7 Soft
Processor Available with or without Debug
ProASIC3 Product Family
ProASIC3 Devices
ARM7 Devices 1
Cortex-M1 Devices 1
A3P015 A3P030 A3P060 A3P125 A3P250
M1A3P250
A3P400
M1A3P400
A3P600
M1A3P600
A3P1000
M7A3P1000
M1A3P1000
System Gates
15 k 30 k 60 k 125 k 250 k
400 k
600 k
1M
Typical Equivalent Macrocells
128 256 512 1,024
–
–
–
–
VersaTiles (D-flip-flops)
384
768 1,536 3,072
6,144
9,216
13,824
24,576
RAM kbits (1,024 bits)
– – 18 36 36 54 108 144
4,608-Bit Blocks
– –48
8
12
24
32
FlashROM Bits
Secure (AES) ISP 2
1k 1k 1k 1k
1k
1k
1k
1k
–
– Yes Yes
Yes
Yes
Yes
Yes
Integrated PLL in CCCs
VersaNet Globals 3
– –11
1
1
1
1
6 6 18 18 18
18
18
18
I/O Banks
2 222
4
4
4
4
Maximum User I/Os
49 81 96 133 157
194
235
300
Package Pins
QFN
VQFP
TQFP
PQFP
FBGA
QN68
QN132
VQ100
QN132
VQ100
TQ144
FG144
QN132
VQ100
TQ144
PQ208
FG144
QN132 5
VQ100
PQ208
FG144/256 5
PQ208
FG144/256/
484
PQ208
FG144/256/
484
PQ208
FG144/256/
484
Notes:
1. Refer to the CoreMP7 datasheet or Cortex-M1 product brief for more information.
2. AES is not available for ARM-enabled ProASIC3 devices.
3. Six chip (main) and three quadrant global networks are available for A3P060 and above.
4. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs handbook.
5. The M1A3P250 device does not support this package.
† A3P015 and A3P030 devices do not support this feature.
February 2008
© 2008 Actel Corporation
‡ Supported only by A3P015 and A3P030 devices.
I
I/Os Per Package 1
www.DataSheet4U.com
ProASIC3
Devices
A3P015
ARM7 Devices
Cortex-M1
Devices
A3P030
A3P060
A3P125
A3P250 3
M1A3P250 3,6
I/O Type
A3P400 3
M1A3P400 3
A3P600
M1A3P600
A3P1000
M7A3P1000
M1A3P1000
Package
QN68
49 – – – – – – –
–––
QN132
– 81 80 84 87 19 – –
–––
VQ100
– 77 71 71 68 13 – –
–––
TQ144
– – 91 100 – – – – – – – –
PQ208
– – – 133 151 34 151 34 154 35 154 35
FG144
– – 96 97 97 24 97 25 97 25 97 25
FG256
– – – – 157 38 178 38 177 43 177 44
FG484
– – – – – – 194 38 235 60 300 74
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 Flash Family FPGAs
handbook to ensure complying with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer
to the ProASIC3 Flash Family FPGAs handbook for position assignments of the 15 LVPECL pairs.
4. FG256 and FG484 are footprint-compatible packages.
5. "G" indicates RoHS-compliant packages. Refer to "ProASIC3 Ordering Information" on page III for the location of the
"G" in the part number.
6. The M1A3P250 device does not support FG256 or QN132 packages.
Table 1-1 • ProASIC3 FPGAs Package Sizes Dimensions
Package
QN68
QN132 VQ100
Length × Width
(mm \ mm)
8×8
8×8
14 × 14
Nominal Area
(mm2)
64 64 196
Pitch (mm)
0.4 0.5 0.5
Height (mm)
0.90 0.75 1.00
TQ144
20 × 20
400
0.5
1.40
PQ208
28 × 28
784
0.5
3.40
FG144
13 × 13
169
1.0
1.45
FG256
17 × 17
289
1.0
1.60
FG484
23 × 23
529
1.0
2.23
II v1.0
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