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TMOS POWER FET 1.0 AMPERE 500 VOLTS



Motorola Semiconductors 로고
Motorola Semiconductors
MTD1N50E 데이터시트, 핀배열, 회로
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Designer's
Data Sheet
TMOS E-FET .
Power Field Effect Transistor
DPAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add –T4 Suffix to Part Number
G
®
D
S
Order this document
by MTD1N50E/D
MTD1N50E
Motorola Preferred Device
TMOS POWER FET
1.0 AMPERE
500 VOLTS
RDS(on) = 5.0 OHM
CASE 369A–13, Style 2
DPAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
500
Vdc
Drain–to–Gate Voltage (RGS = 1.0 M)
VDGR
500
Vdc
Gate–to–Source Voltage — Continuous
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— Non–repetitive (tp 10 ms)
VGS
VGSM
±20
±40
Vdc
Vpk
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (tp 10 µs)
ID 1.0 Adc
ID 0.8
IDM 3.0 Apk
Total Power Dissipation @ TC = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C, when mounted to minimum recommended pad size
PD 40 Watts
0.32 W/°C
1.75 Watts
Operating and Storage Temperature Range
TJ, Tstg – 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, IL = 3.0 Apk, L = 10 mH, RG = 25 )
EAS
45
mJ
Thermal Resistance — Junction to Case
RθJC 3.13 °C/W
— Junction to Ambient
RθJA
100
— Junction to Ambient, when mounted to minimum recommended pad size
RθJA
71.4
Maximum Temperature for Soldering Purposes, 1/8from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
© MMoototororloa,laIncT.M19O95S Power MOSFET Transistor Device Data
1


MTD1N50E 데이터시트, 핀배열, 회로
MTD1N50E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
500
480
— Vdc
— mV/°C
Zero Gate Voltage Drain Current
(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
IDSS
IGSS
µAdc
— — 10
— — 100
— — 100 nAdc
VGS(th)
2.0 3.2 4.0 Vdc
— 6.0 — mV/°C
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 0.5 Adc)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 1.0 Adc)
(ID = 0.5 Adc, TJ = 125°C)
Forward Transconductance (VDS = Vdc, ID = 0.5 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(VDS = 25 Vdc, VGS = 10 Vdc,
f = 1.0 MHz)
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
(VDD = 250 Vdc, ID = 1.0 Adc,
VGS = 10 Vdc,
RG = 9.1 )
Gate Charge
(See Figure 8)
(VDS = 400 Vdc, ID = 1.0 Adc,
VGS = 10 Vdc)
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SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
(IS = 1.0 Adc, VGS = 0 Vdc)
(IS = 1.0 Adc, VGS = 0 Vdc, TJ = 125°C)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
— 4.3 5.0 Ohm
Vdc
— 4.5 6.0
— — 5.3
0.5 0.9
— mhos
— 215 315 pF
— 30.2 42
— 6.7 12
— 8.0 20 ns
— 9.0 10
— 14 30
— 17 30
— 7.4 9.0 nC
— 1.6 —
— 3.8 —
— 5.0 —
Vdc
— 0.81 1.2
— 0.68 —
Reverse Recovery Time
(See Figure 14)
(IS = 1.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25from package to center of die)
trr
ta
tb
QRR
LD
— 141 —
— 82 —
— 58.5 —
— 0.65 —
— 3.5 —
— 4.5 —
ns
µC
nH
Internal Source Inductance
(Measured from the source lead 0.25from package to source bond pad)
LS
— 7.5 — nH
(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
(2) Switching characteristics are independent of operating junction temperature.
2 Motorola TMOS Power MOSFET Transistor Device Data




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