MTD15N06V 반도체 회로 부품 판매점
TMOS POWER FET 15 AMPERES 60 VOLTS
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 Motorola Semiconductors |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MTD15N06V/D
Designer's
™ Data Sheet
TMOS V
Power Field Effect Transistor
DPAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resis-
tance area product about one–half that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
MTD15N06V
Motorola Preferred Device
TMOS POWER FET
15 AMPERES
60 VOLTS
RDS(on) = 0.12 OHM
TM
D
New Features of TMOS V
• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
• Faster Switching than E–FET Predecessors
G
CASE 369A–13, Style 2
DPAK Surface Mount
S
Features Common to TMOS V and TMOS E–FETS
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and TMOS E–FET
• Surface Mount Package Available in 16 mm 13–inch/2500 Unit Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
VDSS
60
Vdc
Drain–Gate Voltage
www.DataSheet4U.com
(RGS
=
1.0
MΩ)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Single Pulse (tp ≤ 50 ms)
VDGR
VGS
VGSM
60
± 20
± 25
Vdc
Vdc
Vpk
Drain Current — Continuous @ 25°C
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID 15 Adc
ID 8.7
IDM 45 Apk
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C, when mounted to minimum recommended pad size
PD 55 Watts
0.36 W/°C
2.1 Watts
Operating and Storage Temperature Range
TJ, Tstg – 55 to 175
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 15 Apk, L = 1.0 mH, RG = 25 Ω)
EAS
113
mJ
Thermal Resistance — Junction to Case
RθJC 2.73 °C/W
Thermal Resistance — Junction to Ambient
RθJA
100
Thermal Resistance — Junction to Ambient, when mounted to minimum recommended pad size
RθJA
71.4
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
© MMoototororloa,laIncT.M19O96S Power MOSFET Transistor Device Data
1
MTD15N06V
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
60 — — Vdc
— 67 — mV/°C
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
IDSS
IGSS
µAdc
— — 10
— — 100
— — 100 nAdc
VGS(th)
2.0 2.7 4.0 Vdc
— 5.0 — mV/°C
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 7.5 Adc)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 15 Adc)
(ID = 7.5 Adc, TJ = 150°C)
Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
(VDD = 30 Vdc, ID = 15 Adc,
VGS = 10 Vdc,
RG = 9.1 Ω)
Gate Charge
(See Figure 8)
(VDS = 48 Vdc, ID = 15 Adc,
VGS = 10 Vdc)
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SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
(IS = 15 Adc, VGS = 0 Vdc)
(IS = 15 Adc, VGS = 0 Vdc, TJ = 150°C)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
— 0.08 0.12 Ohm
Vdc
— 2.0 2.2
— — 1.9
4.0 6.2
— mhos
— 469 660 pF
— 148 200
— 35 60
— 7.6 20 ns
— 51 100
— 18 40
— 33 70
— 14.4 20
nC
— 2.8 —
— 6.4 —
— 6.1 —
Vdc
— 1.05 1.6
— 1.5 —
Reverse Recovery Time
(See Figure 14)
(IS = 15 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
trr
ta
tb
QRR
LD
— 59.3 —
— 46 —
— 13.3 —
— 0.165 —
— 4.5 —
ns
µC
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
— 7.5 — nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
2 Motorola TMOS Power MOSFET Transistor Device Data
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