IS43DR16320B 반도체 회로 부품 판매점
512Mb DDR2 SDRAM
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 ISSI |
IS43DR86400B, IS43/46DR16320B
512Mb (x8, x16) DDR2 SDRAM
FEATURES
PRELIMINARY INFORMATION
DECEMBER 2009
• Clock frequency up to 400MHz
• Posted CAS
• Programmable CAS Latency: 3, 4, 5 and 6
• Programmable Additive Latency: 0, 1, 2, 3, 4 and 5
• Write Latency = Read Latency‐1
• Programmable Burst Sequence: Sequential or
Interleave
• Programmable Burst Length: 4 and 8
• Automatic and Controlled Precharge Command
• Power Down Mode
• Auto Refresh and Self Refresh
• Refresh Interval: 7.8 μs (8192 cycles/64 ms)
• OCD (Off‐Chip Driver Impedance Adjustment)
• ODT (On‐Die Termination)
• Weak Strength Data‐Output Driver Option
• Bidirectional differential Data Strobe (Single‐
ended data‐strobe is an optional feature)
• On‐Chip DLL aligns DQ and DQs transitions with
CK transitions
• Differential clock inputs CK and CK#
• VDD and VDDQ = 1.8V ± 0.1V
• PASR (Partial Array Self Refresh)
• SSTL_18 interface
• tRAS lockout supported
• Read Data Strobe supported (x8 only)
• Internal four bank operations with single pulsed
RAS
• Operating temperature:
Commercial (TA = 0°C to +70°C ; TC = 0°C to 85°C)
Industrial (TA = ‐40°C to +85°C; TC = ‐40°C to 95°C)
Automotive, A1 (TA = ‐40°C to +85°C; TC = ‐40°C to
95°C)
OPTIONS
• Configuration:
− 64Mx8 (16M x 8 x 4 banks)
− 32Mx16 (8M x 16 x 4 banks)
• Package:
− 60‐ball FBGA for x8
www.Da−taSh8e4e‐t4bUa.lcl oFmBGA for x16
ADDRESS TABLE
Parameter
Row Addressing
Column Addressing
Bank Addressing
Precharge Addressing
64Mx8
A0‐A13
A0‐A9
BA0‐BA1
A10
32Mx16
A0‐A12
A0‐A9
BA0‐BA1
A10
Clock Cycle Timing
Speed Grade
CL‐tRCD‐tRP
tCK (CL=3)
tCK (CL=4)
tCK (CL=5)
‐5B
DDR2‐400B
3‐3‐3
5
5
5
‐37C
DDR2‐533C
4‐4‐4
5
3.75
3.75
‐3D
DDR2‐667D
5‐5‐5
5
3.75
3
‐25E
DDR2‐800E
6‐6‐6
5
3.75
3
‐25D
DDR2‐800D
5‐5‐5
5
3.75
2.5
Units
tCK
ns
ns
ns
tCK (CL=6) 5 3.75 3 2.5 2.5 ns
Frequency (max)
200
266
333
400
400 MHz
Note: The ‐5B device specification is shown for reference only.
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00B, 12/11/2009
1
IS43DR86400B, IS43/46DR16320B
Package Ball‐out and Description
DDR2 SDRAM (64Mx8) BGA Ball‐out (Top‐View) (10.00 mm X 10.50 mm Body, 0.8 mm pitch)
123456789
A
VDD RDQS VSS
B
DQ6 VSSQ DM/RDQS
C
VDDQ DQ1 VDDQ
D
DQ4 VSSQ DQ3
E
VDDL VREF VSS
F
CKE WE
G
NC BA0 BA1
H
A10 A1
J
VSS A3 A5
K
A7 A9
L
VDD A12 NC
Symbol
CK, CK#
CKE
CS#
www.DataSheet4U.cRoAmS#,CAS#,WE#
Ax
BAx
DQx
DQS, DQS#
RDQS, RDQS#
DM
VDD
VSS
VDDQ
VSSQ
VREF
VDDL
VSSDL
ODT
NC
Description
Input clocks
Clock enable
Chip Select
Command control pins
Address
Bank Address
I/O
Data Strobe
Redundant Data Strobe
Input data mask
Supply voltage
Ground
DQ power supply
DQ ground
Reference voltage
DLL power supply
DLL ground
On Die Termination Enable
No connect
VSSQ DQS VDDQ
DQS VSSQ DQ7
VDDQ DQ0 VDDQ
DQ2 VSSQ DQ5
VSSDL LDQS VDD
RAS CK ODT
CAS CS
A2 A0 VDD
A6 A4
A11 A8 VSS
NC A13
Not populated
Notes:
1. Pins B3 and A2 have identical capacitance as pins B7
and A8.
2. For a read, when enabled, strobe pair RDQS & RDQS#
are identical in function and timing to strobe pair DQS &
DQS# and input masking function is disabled.
3. The function of DM or RDQS/RDQS# are enabled by
EMRS command.
4. VDDL and VSSDL are power and ground for the DLL. It
is recommended that they are isolated on the device
from VDD, VDDQ, VSS, and VSSQ.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00B, 12/11/2009
2
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