ATV5000 반도체 회로 부품 판매점
High Density UV Erasable Programmable Logic Device
|
|
 ATMEL Corporation |
ATV5000/L
Features
•wwAwd.DvaatanScheedetP4Uro.cgomrammable Logic Device - High Gate Utilization
• Flexible Interconnect Architecture - Universal Routing
• Flexible Logic Cells - 128 Flip-Flops and 52 Latches
• Multiple Flip-Flop Types - Synchronous or Asynchronous Registers
• High Speed - 50 MHz Operation
• Complete Third Party Software Support
No Placement, Routing or Layout Software Required
• Proven and Reliable High Speed CMOS EPROM Process
2000 V ESD Protection
200 mA Latchup Immunity
• Reprogrammable - Tested 100% for Programmability
• Commercial, Industrial and Military Temperature Grades
Block Diagram
52 INPUT
LATCHES
8
INPUT
PINS
UNIVERSAL
AND
REGIONAL
INTERCONNECT
52 LOGIC CELLS
(104 FLIP-FLOPS)
24 BURIED CELLS
(24 FLIP-FLOPS)
52
I/O
PINS
High Density
UV Erasable
Programmable
Logic Device
Description
The Atmel V5000 is an easy to use, high density programmable logic device. Its simple, regu-
lar architecture translates into increased utilization and high performance.
The ATV5000 has one programmable combinatorial logic array. This guarantees easy inter-
connection of and uniform performance from all nodes. "Sum terms", which are easy to use
groupings of AND-OR gates, provide combinatorial logic blocks. Sum terms can be wire-
OR’d together to integrate larger logic blocks. To expand the levels of logic, buried sum terms
feed back into the logic array. The 52 I/O pins can each be driven by a register or a sum term.
Each I/O pin has an individually enabled input latch.
All 128 registers are configurable as D- or T-types without using extra logic gates. Individual
sum terms, asynchronous presets, resets and clocks give each flip-flop added flexibility. A
direct "clock from pin" option guarantees synchronization and fast clock to output perform-
ance.
Standard, off-the-shelf third-party software tools and programmers support the ATV5000.
This minimizes start-up investment and improves product support.
Chip Carrier
Pin Configuration
Pin Name
IN
Pins 2,32,36,66
Pins 1,34,35,68
I/O
VCC
Function
Logic and Clock Inputs
Input/Register Clocks 1-4
Input/Latch Clocks 1-4
Bidirectional Buffers
+5 V Supply
JLCC
VCC GND
I/Os IN IN I/Os
1
I/Os I/Os
GND
I/Os 18
VCC
VCC
52 I/Os
GND
I/Os
35
I/Os IN IN
GND VCC
I/Os
I/Os
0065B
1-193
Absolute Maximum Ratings*
www.DataSheet4U.com
Temperature Under
Bias................. -55oC
to
+125oC
Storage Temperature......................-65oC to +150oC
Voltage on Any Pin with
Respect to Ground..........................-2.0 V to +7.0 V1
Voltage on Input Pins
with Respect to Ground
During Programming.....................-2.0 V to +14.0 V1
Programming Voltage with
Respect to Ground........................-2.0 V to +14.0 V1
Integrated UV Erase Dose .............. 7258 W•sec/cm2
*NOTICE: Stresses beyond those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions beyond those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect de-
vice reliability.
Note:
1. Minimum voltage is -0.6 V dc which may undershoot to -2.0 V
for pulses of less than 20 ns. Maximum output pin voltage is
VCC+0.75 V dc which may overshoot to +7.0 V for pulses of less
than 20 ns.
Functional Logic Diagram Description
There are 52 identical input/ouput logic cells and 24 identical
buried logic cells in the ATV5000. Each I/O cell has two flip-
flops, up to three sum terms, individual clock, reset, and preset
terms per flip-flop, and one output enable term. Independent of
output configuration, all flip-flops are always usable, and have
at least four product term inputs each.
Each I/O pin (52 total) signal or its latched version drives the
logic array. There is one latch clock per quadrant.
The ATV5000 has four identical quadrants (see Figure 2). The
universal bus routes true and false signals from each of the 52
I/O pins to all four quadrants. Regional buses route each quad-
rant’s flip-flop Q and Q locally. The eight input-only pins are
available in all four regional buses.
Each logic cell has a number of "regional" and "universal" prod-
uct terms (see Figure 1). The I/O logic cells contain three sum
terms, two flip-flops, and an I/O buffer.
The buried logic cells each contain one flip-flop. In addition, in
each buried logic cell the sum term can drive the regional bus.
This allows for logic expansion.
Serial register preload and observability simplify testing. All
registers automatically clear at power up.
Quadrant Functional Logic
Diagram ATV5000
UNIVERSAL BUS
TO ALL
QUADRANTS
UNIVERSAL INPUTS
UNIVERSAL
PRODUCT
TERMS
REGIONAL
PRODUCT
TERMS
INPUT/OUTPUT
LOGIC CELLS
(13 TOTAL
PER QUADRANT)
I/O
PINS
REGIONAL INPUTS
UNIVERSAL
PRODUCT
TERMS
REGIONAL
PRODUCT
TERMS
REGISTERCLOCKS
REGISTERCLOCKS
INPUT
PINS
BURIED
LOGIC CELLS
(6 TOTAL
PER QUADRANT)
REGIONAL INPUTS
REGIONAL
BUS
Figure 1
D.C. and A.C. Operating Range
Operating Temperature (Case)
VCC Power Supply
ATV5000-25
Commercial
0oC - 70oC
5 V ± 5%
1-194 ATV5000/L
ATV5000/L-30
Industrial
0oC - 70oC
5 V ± 10%
ATV5000/L-35
Military
-55oC - 125oC
5 V ± 10%
|
PDF 파일 내의 페이지 : 총 13 페이지
제조업체: ATMEL Corporation
( atmel )
ATV5000 data
데이터시트 다운로드 :
[ ATV5000.PDF ]
[ ATV5000 다른 제조사 검색 ]
국내 전력반도체 판매점
상호 : 아이지 인터내셔날
전화번호 : 051-319-2877
[ 홈페이지 ]
IGBT, TR 모듈, SCR, 다이오드모듈, 각종 전력 휴즈
( IYXS, Powerex, Toshiba, Fuji, Bussmann, Eaton )
전력반도체 문의 : 010-3582-2743
관련 데이터시트
ATV5000
High Density UV Erasable Programmable Logic Device - ATMEL Corporation
ATV5000L
High Density UV Erasable Programmable Logic Device - ATMEL Corporation