DZ80 반도체 회로 부품 판매점
8-bit Microprocessor
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 Digital Core Design |
www.DataSheet4U.com
DZ80
8-bit Microprocessor
ver 1.00
OVERVIEW
Document contains brief description of DZ80
core functionality. The DZ80 is an advanced 8-
bit microprocessor with 208 bits of user acces-
sible registers, composed of six general pur-
pose registers, able to be used individually as
either 8-bit registers, or as 16-bit register pairs.
Additionally to those registers, DZ80 supports
two sets of accumulator and flag registers.
The DZ80 contains also Stack Pointer, program
Counter, two index registers, a REFRESH reg-
ister, and an INTERRUPT register. All output
signals are fully decoded and timed to control
standard memory or peripheral circuits. The
DZ80 is supported by a wide range of peripher-
als family.
DZ80 is fully customizable, which means it is
delivered in the exact configuration to meet
users requirements. There is no need to pay
extra for not used features and wasted silicon. It
includes fully automated testbench with
complete set of tests allowing easy package
validation at each stage of SoC design flow.
CPU FEATURES
● Fully compatible with industry standard Z80
● Fully synthesizable, static synchronous de-
sign with no internal tri-states
● No internal reset generator or gated clock
● Scan test ready
● Technology independent HDL source code
● Core can be fully customized
DESIGN FEATURES
♦ ONE GLOBAL SYSTEM CLOCK
♦ SYNCHRONOUS RESET
♦ ALL ASYNCHRONOUS INPUT SIGNALS ARE
SYNCHRONIZED BEFORE INTERNAL USE
♦ ALL LATHES IMPLEMENTED IN ORIGINAL Z80
MICROCONTROLLER ARE REPLACED BY
EQUIVALENT FLI-FLOPS.
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2006 DCD – Digital Core Design. All Rights Reserved.
DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF
♦ VHDL & VERILOG test bench environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
www.DataShe♦et4US.coymnthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
● Delivery the IP Core updates, minor and
major versions changes
● Delivery the documentation updates
○ Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC implementa-
tion.
Unlimited Designs, One Year licenses allow use
IP Core in unlimited number of FPGA bit-
streams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restriction
except One Year license where time of use is
limited to 12 months.
● Single Design license for
○ VHDL, Verilog source code called HDL Source
○ Encrypted, or plain text EDIF called Netlist
● Unlimited Designs license for
○ HDL Source
○ Netlist
● Upgrade from
○ HDL Source to Netlist
○ Single Design to Unlimited Designs
PINS DESCRIPTION
PIN
clk
rst
int
nmi
wait
busreq
datai[7:0]
datao[7:0]
addr[15:0]
wr
rd
busack
m1
mreq
iorq
rfsh
halt
ACTIVE TYPE
DESCRIPTION
- input Global system clock
Low input Global reset input
Low input Interrupt request
Low input Non-Maskable Interrupt Request
Low input WAIT input
Low input Bus Request
- input Memory bus input
- output Data memory & UFR bus output
- output Data memory address bus
Low output Write enable
Low output Read enable
Low output Bus Acknowledge
Low output Machine Cycle One
Low output Memory Request
Low output Input/Output Request
Low output Refresh
Low output Halt State
SYMBOL
clk
rst
datai(7:0)
int
nmi
busrq
wait
halt
datao(7:0)
addr(15:0)
wr
rd
m1
mreq
iorq
rfsh
busack
BLOCK DIAGRAM
Control Unit - Performs the core synchroniza-
tion and data flow control. This module man-
ages execution of all instructions. The Control
Unit also manages execution of HALT state and
waking-up the processor from the HALT mode.
Opcode Decoder - Performs an instruction
opcode decoding and the control functions for
all other blocks.
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2006 DCD – Digital Core Design. All Rights Reserved.
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DZ80 data
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[ DZ80.PDF ]
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