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SEMICONDUCTOR TECHNICAL DATA
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Twisted Pair Interface
for FDDI Local Area Networks
MC68835
Overview
The FDDI is a LAN standard under ANSI auspices. The standard
supports a 100 Mbps fiber–optic–based token ring with up to 1000
stations; total ring length should not exceed 200 Km with up to 2 km
between stations. FDDI over twisted–pair cable is also supported by the
TP–PMD standard. The twisted pair cable connecting two stations can be
up to 100 meters in length. Users are encouraged to refer to the pertinent
ANSI standard documents for further information.
Introduction
The MC68835 Twisted–Pair Interface chip (TPIC) is a transceiver
capable of transmitting and receiving MLT3 or NRZI encoded data
streams, as well as handling clock and data recovery. The TPIC
FA SUFFIX
TQFP PACKAGE
CASE 931–02
implements the lower portion of the Physical layer (PHY) functions of the
FDDI standard. It performs a five–bit parallel to serial conversion during
transmission, as well as a five–bit serial to parallel conversion during
reception. The TPIC uses the five–bit parallel interface to communicate with the MC68837 Elastic Buffer and Link Manager
(ELM) device or other Motorola FDDI devices that incorporate the ELM function internally, such as the 68840 IFDDI, 68848
CAMEL, or the 68847 Quad ELM.
MC68835 Features
• Supports Twisted Pair and Fiber Optic Media
• Supports MLT–3 Line Code in Twisted Pair Mode
• Supports NRZI Line Code in Fiber Mode
• Adaptive Receive Equalization supports TP line lengths of 0 to 100 meters
• Controlled Twisted Pair Output Transition Times May Eliminate Need for Transmit Filter
• TP Receiver Includes Circuitry Which Enables Error Free Reception of Data Distorted with Base Line Wander
• Twisted Pair and Fiber Transmitters Share Same IC pins. Twisted Pair and Fiber Receivers also Share Same IC Pins
• Twisted Pair or Fiber Optic Operation Selected with PORTSEL Input
• Twisted Pair (TP) Transceiver Complies with ANSI X3T9.5 TP–PMD FDDI Standard
• Meets Jitter Requirements of ANSI X3T9.5 TP–PMD
• Pseudo–ECL Interface For Fiber–Optic Media
• Digital Phase–Locked Loop (DPLL) Provides Run Length Immunity
• Transmit Off Capability for True Quiet Line State
• Uses a 25 Mhz External Frequency Reference
• Converts Received Serial Bit Stream to Five–Bit Parallel Form
• Recovers 125 Mhz Clock from Incoming Serial NRZI or MLT3 Data Stream
• Generates 25 Mhz Receive Clock
• Small Number of Passive External Components Required
• Selectable Low Power Mode
• Loop Back Capability
• Single +5V Power Supply
• Utilizes 0.8uM BiCMOS Technology
• 10mM X 10mM, 64 Pin, TQFP Package
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
4/95
© Motorola, Inc. 1995
REV 1.3
www.DMataCS6he8e8t43U5.com
Functional Description
SD
ELM
MC68835
TDH
TDH
RSCLK
TDL TDL
RDATAx
RDH TRANSFORMERS
TP
RDH CONNECTOR
TDATAx
RDL
RDL
Figure 1. Simplified Block Diagram for Twisted Pair Applications of the MC68835 TPIC
SDH SDH
SD
SDL SDL
ELM
RSCLK
MC68835
TDH
FIBER
TDH
RDATAx
INTERFACE
TDL COMPONENTS
FIBER
TDL CONNECTOR
RDH RDH
TDATAx
RDL
RDL
Figure 2. Simplified Block Diagram for Optical Fiber Applications of the MC68835 TPIC
MOTOROLA
2
TIMING SOLUTIONS
BR1333 — REV 4
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