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P1817A 반도체 회로 부품 판매점

Low-Power Mobile VGA EMI Reduction IC



Alliance Semiconductor 로고
Alliance Semiconductor
P1817A 데이터시트, 핀배열, 회로
www.DataSheet4U.com
October 2003
P1817A/B
rev 1.0
Low-Power Mobile VGA EMI Reduction IC
Features
FCC approved method of EMI attenuation.
Generates a low EMI spread spectrum clock of the
input frequency.
Optimized for frequency range from:
o P1817A – 20 to 30MHz. Operation
o P1817B – 10 to 20MHz Operation
Internal loop filter minimizes external components
and board space.
Two selectable spread ranges.
Low inherent cycle-to-cycle jitter.
3.3V or 5V operating voltage range.
TTL or CMOS compatible outputs.
Ultra-low power CMOS design.
3.17mA @3.3V, 10MHz | [email protected], 10MHz
4.28mA @3.3V, 14MHz | 7.50mA @5.0V, 14MHz
5.50mA @3.3V, 20MHz | 9.50mA @5.0V, 20MHz
Supports notebook VGA and other LCD timing
controller applications.
SSON pin for Spread Spectrum On/Off and
Standby Mode controls.
Available in 8-pin SOIC and TSSOP.
Product Description
The P1817 is a versatile spread spectrum frequency
modulator designed specifically for input clock frequencies.
The P1817 reduces electromagnetic interference (EMI) at
the clock source, allowing system wide reduction of EMI of
down stream clock and data dependent signals. The P1817
allows significant system cost savings by reducing the
number of circuit board layers ferrite beads, shielding and
other passive components that are traditionally required to
pass EMI regulations.
The P1817 modulates the output of a single PLL in order to
“spread” the bandwidth of a synthesized clock, and more
importantly, decreases the peak amplitudes of its
harmonics. This results in significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most frequency generators. Lowering EMI
by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’.
The P1817 uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all digital method.
Applications
The P1817 is targeted towards notebook VGA chip and
other displays using an LVDS interface, PC peripheral
devices, and embedded systems.
Block Diagram
SR0 SSON
VDD
XIN
XOUT
Crystal
Oscillator
Ref
Frequency
Divider
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
PLL
VCO
Output
Divider
ModOUT
VSS
Alliance Semiconductor
2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.


P1817A 데이터시트, 핀배열, 회로
www.DataSheet4U.com
October 2003
rev 1.0
Pin Configuration
XIN /CLKIN
VSS
SR0
SSON/SBM
1
2
3
4
P1817A/B
8 XOUT
7 VDD
6 REF
5 ModOUT
P1817A/B
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin Name
XIN/CLKIN
VSS
SR0
SSON/SBM
ModOUT
REF
VDD
XOUT
Type
I
P
I
I
O
O
P
O
Description
Connect to externally generated clock signal. To put the part into standby
mode, disable the input clock signal to this pin and pull SSON/SBM (pin 4)
low. Refer Standby Mode Selection Table.
Ground Connection. Connect to system ground.
Digital logic input used to select Spreading Range. Refer Spread Spectrum
Selection Table. This pin has an internal pull-up resistor.
Spread Spectrum On/Off and standby mode control. Refer Standby Mode
Selection Table.
Spread spectrum clock output or reference output. Refer Standby Mode
Selection Table.
Reference output.
Connect to +3.3V or 5.0V.
Connect to crystal. No connect if externally generated clock signal is used.
Low Frequency EMI Reduction
Notice: The information in this document is subject to change without notice.
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