MPC859T 반도체 회로 부품 판매점
Technical Summary
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 Motorola Semiconductors |
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Advance Information
MPC859TTS/D
Rev. 1.2, 4/2003
MPC859P/859T/859DSL
PowerQUICC™
Family Technical Summary
Freescale Semiconductor, Inc.
This document provides an overview of the MPC859P/859T/859DSL PowerQUICC™
Family, describing major functions and features. The MPC859P/859T/859DSL PowerQUICC
Family contains a PowerPC™ processor core. The topics covered include:
Section
Page
Section 1.1, “Features”
2
Section 1.2, “Embedded MPC8xx Core”
6
Section 1.3, “System Interface Unit (SIU)”
7
Section 1.4, “PCMCIA Controller”
8
Section 1.5, “Power Management”
8
Section 1.6, “Communications Processor Module (CPM)”
8
Section 1.7, “ATM Capabilities”
8
Section 1.8, “Differences between MPC859P/859T and MPC859DSL”
9
Section 1.9, “Document Revision History”
9
The MPC859P/859T/859DSL PowerQUICC Family is a 0.18 micron version of the MPC860
PowerQUICC Family and can operate up to 133 MHz on the MPC8xx Core with a 66 MHz
external bus. The MPC866 Family has a 1.8 V core and has a 3.3 V I/O operation with 5 V
TTL compatibility. The MPC859P/859T/859DSL Integrated Communications Controller
Family is a versatile one-chip integrated microprocessor and peripheral combination that can
be used in a variety of controller applications. It particularly excels in both communications
and networking systems.
The MPC859P/859T/859DSL Family is a PowerPC architecture-based derivative of
Motorola’s MPC860 Quad Integrated Communications Controller (PowerQUICC). The CPU
on the MPC859P/859T/859DSL is the MPC8xx core, a 32-bit microprocessor which
implements the PowerPC architecture, incorporating memory management units (MMUs) and
instruction and data caches. The MPC859P is mainly described in this document.
Table 1 shows the functionality supported by the members of the MPC859P family:
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Features
Freescale Semiconductor, Inc.
Part
MPC859P
Table 1. MPC859T Family
Cache
Instruction
Cache
16 Kbyte
Data Cache
8 Kbyte
Ethernet
10Base
T
10/100
11
SCC
1
MPC859T
4 Kbyte
4 Kbyte
111
MPC859DSL 4 Kbyte
4 Kbyte
111
ATM Support
Serial ATM and UTOPIA
Interface
Serial ATM and UTOPIA
Interface
Serial ATM and UTOPIA
Interface
1.1 Features
The following list summarizes the key MPC859P/859T/859DSL Family features:
• Embedded MPC8xx core up to 133 MHz
• Maximum frequency operation of the external bus is 66 MHz
— The 133MHz/100MHz core frequencies support 2:1 mode only
— The 50MHz/66MHz core frequencies support both 1:1 and 2:1 modes
• Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with 32, 32-bit
general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1).
– 16-Kbyte instruction cache (MPC859P) is four-way, set-associative with 256 sets;4-Kbyte
instruction cache (MPC859T and MPC859DSL) is two-way, set-associative with 128 sets.
– 8-Kbyte data cache (MPC859P) is two-way, set-associative with 256 sets; 4-Kbyte data
cache (MPC859T and MPC859DSL) is two-way, set-associative with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces and 16 protection groups
• The MPC859P/859T/859DSL Family provides enhanced ATM functionality as found on the
MPC866. The MPC859P/859T/859DSL adds major new features available in “enhanced SAR”
(ESAR) mode, including the following:
— Improved operation, administration and maintenance (OAM) support
— OAM performance monitoring (PM) support
— Multiple APC priority levels available to support a range of traffic pace requirements
— Port-to-port switching capability without the need for RAM-based microcode
— Simultaneous MII (100Base-T) and UTOPIA (half-duplex) capability
— Optional statistical cell counters per PHY
2 MPC859P/859T/859DSL PowerQUICC™ FamilyTechnical Summary MOTOROLA
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