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SY100H842 반도체 회로 부품 판매점

SINGLE SUPPLY QUAD PECL-TO-TTL OUTPUT ENABLE



Micrel Semiconductor 로고
Micrel Semiconductor
SY100H842 데이터시트, 핀배열, 회로
www.DataSheet4U.com
SINGLE SUPPLY
QUAD PECL-TO-TTL
OUTPUT ENABLE
ClockWorks™
SY10H842
SY100H842
FEATURES
s Translates positive ECL-to-TTL (PECL-to-TTL)
s 300ps pin-to-pin skew
s 500ps part-to-part skew
s Differential internal design for increased noise
immunity and stable threshold inputs
s VBB reference output
s Single supply
s Enable input
s Extra TTL and ECL power/ground pins to reduce
cross-talk/noise
s High drive capability: 24mA each output
s Fully compatible with industry standard 10K, 100K
I/O levels
s Available in 16-pin SOIC package
DESCRIPTION
The SY10/100H842 are single supply, low skew
translating 1:4 clock drivers.
The devices feature a 24mA TTL output stage, with
AC performance specified into a 50pF load capacitance.
A HIGH on the enable pin (EN) forces all outputs LOW.
As frequencies increase to 40MHz and above, precise
timing and shaping of clock signals becomes extremely
important. The H842 solves several clock distribution
problems such as minimizing skew 300ps), maximizing
clock fanout (24mA drive), and precise duty cycle control
through a proprietary differential internal design.
The 10K version is compatible with 10KH ECL logic
levels. The 100K version is compatible with 100K levels.
BLOCK DIAGRAM
TTL Outputs
Q0
Q1
Q2
ECL Input
D
D
VBB
EN
Q3
PIN CONFIGURATION
GT 1
16 Q3
EN 2
15 GT
GE 3
14 Q2
VE 4 SOIC 13 VT
D 5 Z16-1 12 VT
D6
11 Q1
VBB 7
10 GT
GT 8
9 Q0
PIN NAMES
Pin
GT
VT
VE
GE
D, D
VBB
Q0 - Q3
EN
1
Function
TTL Ground (0V)
TTL VCC (+5.0V)
ECL VCC (+5.0V)
ECL Ground (0V)
Signal Input (PECL)
VBB Reference Output (PECL)
Signal Outputs (TTL)
Enable Input (PECL)
Rev.: E Amendment: /1
Issue Date: August, 1999


SY100H842 데이터시트, 핀배열, 회로
Micrel
ClockWorks™
SY10H842
SY100H842
TRUTH TABLE
PIN DESCRIPTION
D EN
LL
HL
XH
Q
L
H
L
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VE (ECL)
VT (TTL)
VI (ECL)
VOUT (TTL)
Tstore
TA
Rating
Power Supply
Voltage
Input Voltage
Storage Temperature
Operating Temperature
Value
–0.5 to +7.0
–0.5 to +7.0
0.0 to VEE
0.0 to VT
–65 to +150
0 to +85
Unit
V
V
˚C
˚C
NOTE:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS
are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections
of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions
for extended periods may affect device reliability.
Pin Symbol
Description
1 GT TTL Ground (0V)
2 EN Enable Input (PECL)
3 GE ECL Ground (0V)
4 VE ECL VCC (+5.0V)
5 D ECL Signal Input (Non-inverting)
6 D ECL Signal Input (Inverting)
7 VBB VBB Reference Output (PECL)
8 GT TTL Ground (0V)
9 Q0 Signal Output (TTL)
10 GT TTL Ground (0V)
11 Q1 Signal Output (TTL)
12 VT TTL VCC (+5.0V)
13 VT TTL VCC (+5.0V)
14 Q2 Signal Output (TTL)
15 GT TTL Ground (0V)
16 Q3 Signal Output (TTL)
VCC AND CLOAD
Ranges to meet duty cycle requirement: 0°C TA 85°C. Output duty cycle measured relative to 1.5V.
Symbol
Parameter
Min. Typ. Max.
Unit
Condition
PW Ranges of VCC and CL to meet min. VCC 4.75 5.0 5.25 V All Outputs
pulse width (HIGH or LOW) at
CL 10 —
50 pF
fOUT 40MHz
PW 11
— ns
PW
Ranges of VCC and CL to meet min.
VCC 4.875 5.0
5.125
V
All Outputs
pulse width (HIGH or LOW) at
CL 15 —
27 pF
fOUT 50MHz
PW 9.0 —
— ns
DC CHARACTERISTICS
VT = VE = 5.0V ± 5%
Symbol
IEE
ICCH
ICCL
Parameter
Power Supply Current
Power Supply Current
TA = 0°C
TA = +25°C
TA = +85°C
Min. Max. Min. Max. Min. Max. Unit
Condition
ECL — 35 — 35 — 35 mA
VE Pin
TTL — 20 — 20 — 20 mA Total all VT pins
— 25 — 25 — 25
2




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