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MONOLITHIC 5-TAP 3.3V FIXED DELAY LINE



Data Delay Devices 로고
Data Delay Devices
3D3215 데이터시트, 핀배열, 회로
www.DataSheet4U.com
MONOLITHIC 5-TAP 3.3V
FIXED DELAY LINE
(SERIES 3D3215)
3D3215
data
delay
3
®
devices, inc.
FEATURES
All-silicon, low-power 3.3V CMOS technology
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Leading- and trailing-edge accuracy
Delay range: 1.5ns through 300ns
Total delay tolerance: 2% or 0.5ns (3.3V, 25C)
Temperature stability: ±1% typical (0C-70C)
Vdd stability: ±1% typical (3.0V-3.6V)
Static Idd: 1.3ma typical
Minimum input pulse width: 25% of total delay
PACKAGES
IN
O2
O4
GND
18
27
36
45
VDD
O1
O3
O5
3D3215Z-xx
SOIC (150 Mil)
IN
O2
O4
GND
1
2
3
4
8 VDD
7 O1
6 O3
5 O5
3D3215M-xx
DIP (300 Mil)
For mechanical dimensions, click here.
For package marking details, click here.
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D3215 5-Tap Delay Line product family consists of fixed-delay
IN
3.3V CMOS integrated circuits. Each package contains a single delay
O1
line, tapped and buffered at 5 points spaced uniformly in time. Tap-to-
O2
tap (incremental) delay values can range from 1.5ns through 60ns. The
O3
input is reproduced at the outputs without inversion, shifted in time as
O4
per the user-specified dash number. The 3D3215 is 3.3V CMOS-
O5
compatible and features both rising- and falling-edge accuracy.
VDD
GND
The all-CMOS 3D3215 integrated circuit has been designed as a
N/C
reliable, economic alternative to hybrid fixed delay lines. It is offered in a
standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.
Delay Line Input
Tap 1 Output (20%)
Tap 2 Output (40%)
Tap 3 Output (60%)
Tap 4 Output (80%)
Tap 5 Output (100%)
+3.3 Volts
Ground
No Connection
TABLE 1: PART NUMBER SPECIFICATIONS
DASH #
3D3215Z-xx
3D3215M-xx
-1.5
-2
-2.5
-3
-4
-5
-6
-8
-10
-12
-15
-20
-25
-30
-40
-50
-60
DELAY SPECIFICATIONS
TOTAL
DELAY (ns)
TAP-TAP
DELAY (ns)
6.0 ± 0.5*
1.5 ± 0.7
8.0 ± 0.5*
2.0 ± 0.8
10.0 ± 0.5*
12.0 ± 0.5*
2.5 ± 1.0
3.0 ± 1.3
16.0 ± 0.5*
4.0 ± 1.3
20.0 ± 0.5*
5.0 ± 1.4
24.0 ± 0.5*
40.0 ± 0.8
6.0 ± 1.4
8.0 ± 1.4
50.0 ± 1.0
10.0 ± 1.5
60.0 ± 1.2
75.0 ± 1.5
12.0 ± 1.5
15.0 ± 1.5
100 ± 2.0
20.0 ± 2.0
125 ± 2.5
25.0 ± 2.5
150 ± 3.0
200 ± 4.0
30.0 ± 3.0
40.0 ± 4.0
250 ± 5.0
50.0 ± 5.0
300 ± 6.0
60.0 ± 6.0
INPUT RESTRICTIONS
RECOMMENDED
ABSOLUTE
Max Freq Min P.W. Max Freq Min P.W.
23.8 MHz
21.0 ns 83.3 MHz
6.00 ns
20.8 MHz
24.0 ns 83.3 MHz
6.00 ns
18.5 MHz
27.0 ns 66.7 MHz
7.50 ns
16.7 MHz
30.0 ns 55.6 MHz
9.00 ns
13.9 MHz
36.0 ns 50.0 MHz
10.00 ns
11.9 MHz
42.0 ns 40.0 MHz
12.50 ns
10.4 MHz
48.0 ns 55.6 MHz
9.00 ns
8.33 MHz
60.0 ns 41.7 MHz
12.00 ns
6.67 MHz
75.0 ns 40.0 MHz
12.50 ns
5.56 MHz
90.0 ns 33.3 MHz
15.00 ns
4.42 MHz
113 ns 26.7 MHz
18.75 ns
3.33 MHz
150 ns 20.0 MHz
25.00 ns
2.66 MHz
188 ns 16.0 MHz
31.25 ns
2.22 MHz
225 ns 13.3 MHz
37.50 ns
1.67 MHz
300 ns 10.0 MHz
50.00 ns
1.33 MHz
375 ns
8.0 MHz
62.50 ns
1.11 MHz
450 ns
6.7 MHz
75.00 ns
* Total delay referenced to Tap1 output; Input-to-Tap1 = 7.5ns ± 1.5ns
NOTE: Any dash number between 1.5 and 60 not shown is also available as standard
©2001 Data Delay Devices
Doc #01014
12/3/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1


3D3215 데이터시트, 핀배열, 회로
3D3215
APPLICATION NOTES
OPERATIONAL DESCRIPTION
The 3D3215 five-tap delay line architecture is
shown in Figure 1. The delay line is composed of
a number of delay cells connected in series.
Each delay cell produces at its output a replica of
the signal present at its input, shifted in time. The
delay cells are matched and share the same
compensation signals, which minimizes tap-to-tap
delay deviations over temperature and supply
voltage variations.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay accuracy of the particular device. The
reasons for the dependency of the output delay
accuracy on the input signal characteristics are
varied and complex. Therefore a Recommended
Maximum and an Absolute Maximum operating
input frequency and a Recommended Minimum
and an Absolute Minimum operating pulse width
have been specified.
OPERATING FREQUENCY
The Absolute Maximum Frequency
specification, tabulated in Table 1, determines the
highest frequency of the delay line input signal
that can be reproduced, shifted in time at the
device output, with acceptable duty cycle
distortion.
The Recommended Maximum Frequency
specification determines the highest frequency of
the delay line input signal for which the output
delay accuracy is guaranteed. To guarantee the
Table 1 delay accuracy for input frequencies
higher than the Recommended Maximum
Frequency, the 3D3215 must be tested at the
user operating frequency. Therefore, to facilitate
production and device identification, the part
number will include a custom reference
designator identifying the intended frequency of
operation. The programmed delay accuracy of
the device is guaranteed, therefore, only at the
user specified input frequency. Small input
frequency variation about the selected frequency
will only marginally impact the programmed delay
accuracy, if at all. Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
OPERATING PULSE WIDTH
The Absolute Minimum Pulse Width (high or
low) specification, tabulated in Table 1,
determines the smallest Pulse Width of the delay
line input signal that can be reproduced, shifted in
time at the device output, with acceptable pulse
width distortion.
The Recommended Minimum Pulse Width
(high or low) specification determines the
smallest Pulse Width of the delay line input signal
for which the output delay accuracy tabulated in
Table 1 is guaranteed.
To guarantee the Table 1 delay accuracy for input
pulse width smaller than the Recommended
Minimum Pulse Width, the 3D3215 must be
tested at the user operating pulse width.
Therefore, to facilitate production and device
IN O1 O2 O3 O4 O5
IN O1 O2 O3 O4 O5
25% 25% 25% 25%
20% 20% 20% 20% 20%
VDD
Temp & VDD
Compensation
Temp & VDD
Compensation
Dash numbers < 8
GND
VDD
Dash numbers >= 8
Figure 1: 3D3215 Functional Diagram
Doc #01014
12/3/01
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
GND
2




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MONOLITHIC 5-TAP 3.3V FIXED DELAY LINE - Data Delay Devices