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CY62167DV18 반도체 회로 부품 판매점

16M (1024K x 16) Static RAM



Cypress Semiconductor 로고
Cypress Semiconductor
CY62167DV18 데이터시트, 핀배열, 회로
www.DataSheet4U.com
PRELIMINARY
CY62167DV18
MoBL2™
16M (1024K x 16) Static RAM
Features
Very high speed: 55 ns and 70 ns
Voltage range: 1.65V to 1.95V
Ultra-low active power
Typical active current: 1.5 mA @ f = 1 MHz
Typical active current: 15 mA @ f = fMAX
Ultra-low standby power
Easy memory expansion with CE</>1</>, CE2</> and OE</>
features
Automatic power-down when deselected
CMOS for optimum speed/power
Packages offered in a 48-ball FBGA
Functional Description[1]
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected Chip
Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW or both
BHE and BLE are HIGH. The input/output pins (I/O0 through
I/O15) are placed in a high-impedance state when: deselected
Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW,
outputs are disabled (OE HIGH), both Byte High Enable and
Byte Low Enable are disabled (BHE, BLE HIGH) or during a
write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2
(CE2) HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then das
pins (A0 through A19). If Byte High Enable (BHE) is LOW, then
data from I/O pins (I/O8 through I/O15) is written into the
location specified on the ad
The CY62167DV18 is a high-performance CMOS static RAM
organized as 1024K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life(MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
Reading from the device is accomplished by taking Chip
Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and
Output Enable (OE) LOW while forcing the Write Enable (WE)
HIGH. If Byte Low Enable (<>O7. If Byte High Enable (BHE)
is LOW, then data from memory will appear on I/O8 to I/O15.
See the truth table at the back of this data sheet for a complete
description of read and write modes.
DataSheet4U.com
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A 6 1024K x 16
A 5 RAM ARRAY
A 4 2048 x 512 x 16
A3
A2
A1
A0
I/O0–I/O7
I/O8–I/O15
DataShee
COLUMN DECODER
BHE
WE CE2
OE CE1
BLE
Power-down
Circuit
BHE
BLE
CE2
CE1
Note:
1. For best practice recommendations, please refer to the Cypress application note System Design Guidelineson http://www.cypress.com.
DataSheet4U.com
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05326 Rev. *A
Revised February 10, 2003
DataSheet4 U .com


CY62167DV18 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Pin Configuration[2]
PRELIMINARY
FBGA
Top View
12 34 56
BLE OE A0 A1 A2 CE 2
I/O8 BH E A3 A4 CE 1 I/O0
I/O9 I/O10 A5 A6 I/O1 I/O2
VSS I/O11 A17 A7 I/O3 Vcc
VCC I/O12 DNU A16 I/O4 Vss
I/O14 I/O13 A14 A15 I/O5 I/O6
I/O15 A19 A12 A13 WE I/O7
et4U.com
A18 A8 A9 A10 A11 DNU
Note:
2. DNU pins are to be connected to VSS or left open.
DataSheet4U.com
A
B
C
D
E
F
G
H
CY62167DV18
MoBL2
DataShee
DataSheet4U.com
Document #: 38-05326 Rev. *A
DataSheet 4 U .com
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CY62167DV18

16M (1024K x 16) Static RAM - Cypress Semiconductor