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Motorola Semiconductors |
Advance Information
MPC862EC/D
Rev. 1.2, 8/2003
MPC862/857T/857DSL
Hardware Specifications
Freescale Semiconductor, Inc.
This document contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for the MPC862/857T/857DSL family (refer to
Table 1 for a list of devices). The MPC862P, which contains a PowerPC™ core processor, is
the superset device of the MPC862/857T/857DSL family.
This document describes pertinent electrical and physical characteristics of the MPC8245. For
functional characteristics of the processor, refer to the MPC862 PowerQUICC Family Users
Manual (MPC862UM/D).
This document contains the following topics:
Topic
Section 1, “Overview”
Section 2, “Features”
Section 3, “Maximum Tolerated Ratings”
Section 4, “Thermal Characteristics”
Section 5, “Power Dissipation”
Section 6, “DC Characteristics”
Section 7, “Thermal Calculation and Measurement”
Section 8, “Layout Practices”
Section 9, “Bus Signal Timing”
Section 10, “IEEE 1149.1 Electrical Specifications”
Section 11, “CPM Electrical Characteristics”
Section 12, “UTOPIA AC Electrical Specifications”
Section 13, “FEC Electrical Characteristics”
Section 14, “Mechanical Data and Ordering Information”
Section 15, “Document Revision History”
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1 Overview
The MPC862/857T/857DSL is a derivative of Motorola’s MPC860 PowerQUICC™ family of
devices. It is a versatile single-chip integrated microprocessor and peripheral combination that
can be used in a variety of controller applications and communications and networking
systems. The MPC862/857T/857DSL provides enhanced ATM functionality over that of other
ATM-enabled members of the MPC860 family.
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Features
Freescale Semiconductor, Inc.
Table 1 shows the functionality supported by the members of the MPC862/857T/857DSL family.
Table 1. MPC862 Family Functionality
Cache
Ethernet
Part
Instruction
Cache
Data Cache
SCC SMC
10T 10/100
MPC862P
16 Kbyte
8 Kbyte
Up to 4 1
42
MPC862T
4 Kbyte
4 Kbyte
Up to 4 1
42
MPC857T
4 Kbyte
4 Kbyte
1 1 12
MPC857DSL
4 Kbyte
4 Kbyte
1 1 11 12
1 On the MPC857DSL, the SCC (SCC1) is for ethernet only. Also, the MPC857DSL does
not support the Time Slot Assigner (TSA).
2 On the MPC857DSL, the SMC (SMC1) is for UART only.
2 Features
The following list summarizes the key MPC862/857T/857DSL features:
• Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with
thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1).
– 16-Kbyte instruction cache (MPC862P) is four-way, set-associative with 256 sets; 4-Kbyte
instruction cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative
with 128 sets.
– 8-Kbyte data cache (MPC862P) is two-way, set-associative with 256 sets; 4-Kbyte data
cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces and 16 protection groups
— Advanced on-chip-emulation debug mode
• The MPC862/857T/857DSL provides enhanced ATM functionality over that of the MPC860SAR.
The MPC862/857T/857DSL adds major new features available in “enhanced SAR” (ESAR) mode,
including the following:
— Improved operation, administration and maintenance (OAM) support
— OAM performance monitoring (PM) support
— Multiple APC priority levels available to support a range of traffic pace requirements
— ATM port-to-port switching capability without the need for RAM-based microcode
— Simultaneous MII (10/100Base-T) and UTOPIA (half-duplex) capability
2
MPC862/857T/857DSL Hardware Specifications
MOTOROLA
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