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MM24128-BMN5T 반도체 회로 부품 판매점

256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Lines



ST Microelectronics 로고
ST Microelectronics
MM24128-BMN5T 데이터시트, 핀배열, 회로
M24256-B
M24128-B
256/128 Kbit Serial I C Bus EEPROM
With Three Chip Enable Lines
PRELIMINARY DATA
s Compatible with I2C Extended Addressing
s Two Wire I2C Serial Interface
Supports 400 kHz Protocol
s Single Supply Voltage:
– 4.5V to 5.5V for M24xxx-B
– 2.5V to 5.5V for M24xxx-BW
– 1.8V to 3.6V for M24xxx-BR
s Hardware Write Control
s BYTE and PAGE WRITE (up to 64 Bytes)
s RANDOM and SEQUENTIAL READ Modes
s Self-Timed Programming Cycle
s Automatic Address Incrementing
s Enhanced ESD/Latch-Up Behavior
s 100000 Erase/Write Cycles (minimum)
s 40 Year Data Retention (minimum)
DESCRIPTION
These I2C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 32Kx8 bits (M24256-B) and 16Kx8 bits
(M24128-B).
These memory devices are compatible with the
I2C extended memory standard. This is a two wire
serial interface that uses a bi-directional data bus
and serial clock. The memory carries a built-in 4-
bit unique Device Type Identifier code (1010) in
accordance with the I2C bus definition.
Table 1. Signal Names
E0, E1, E2
Chip Enable Inputs
SDA
Serial Data/Address Input/
Output
SCL
Serial Clock
WC Write Control
VCC
Supply Voltage
VSS Ground
8
1
PSDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
14
1
TSSOP14 (DL)
169 mil width
8
1
TSSOP8 (DW)
169 mil width
Figure 1. Logic Diagram
VCC
3
E0-E2
SCL
WC
M24256-B
M24128-B
VSS
SDA
AI02809
February 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/19


MM24128-BMN5T 데이터시트, 핀배열, 회로
M24256-B, M24128-B
Figure 2A. PSDIP8 Connections
Figure 2C. TSSOP14 Connections
M24256-B
M24128-B
E0
E1
E2
VSS
1
2
3
4
8 VCC
7 WC
6 SCL
5 SDA
AI02810
Figure 2B. SO8 and TSSOP8 Connections
E0
E1
E2
VSS
M24256-B
M24128-B
18
27
36
45
AI02811
VCC
WC
SCL
SDA
E0
E1
NC
NC
NC
E2
VSS
M24256-B
M24128-B
1 14
2 13
3 12
4 11
5 10
69
78
AI02812
VCC
WC
NC
NC
NC
SCL
SDA
Note: 1. NC = Not Connected
The memory behaves as a slave device in the I2C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory in-
serts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and af-
ter a NoAck for READ.
Power On Reset: VCC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On Re-
Table 2. Absolute Maximum Ratings 1
Symbol
Parameter
Value
Unit
TA Ambient Operating Temperature
-40 to 125
°C
T STG
TLEAD
Storage Temperature
Lead Temperature during Soldering
PSDIP8: 10 seconds
SO8: 40 seconds
TSSOP8: 40 seconds
TSSOP14: 40 seconds
-65 to 150
260
215
215
215
°C
°C
VIO Input or Output range
-0.6 to 6.5
V
VCC Supply Voltage
-0.3 to 6.5
V
VESD
Electrostatic Discharge Voltage (Human Body model) 2
4000
V
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 )
2/19




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MM24128-BMN5T

256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Lines - ST Microelectronics



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256/128 Kbit Serial IC Bus EEPROM Without Chip Enable Lines - ST Microelectronics