M65667SP 반도체 회로 부품 판매점
PICTURE-IN-PICTURE SIGNAL PROCESSING
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 Mitsubishi |
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI ICs (TV)
M65667SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
DESCRIPTION
The M65667SP is a NTSC PIP (Picture in Picture) signal
processing LSI, whose sub and main-picture inputs are composite
and Y/C separated signals, respectively. The built-in field memory
(96k-bit RAM) ,V-chip data slicer and analog circuitries lead the PIP
system low cost and small size.
FEATURES
• Built-in 96k-bit field memory (sub-picture data storage)
• Internal V-chip data slicer (for sub-picture)
• Pin compatible with M65617SP
• Vertical filter for sub-picture (Y signal )
• Single sub-picture (selectable picture size : 1/9 , 1/16)
• Sub-picture processing sepecification (1/9 size / 1/16 size) :
Quantization bits
Y, B-Y, R-Y : 6bits
Horizontal sampling 171 pixels (Y) , 28.5 pixels (B-Y, R-Y)
Vertical lines
69/ 52 lines
• Frame (sub-picture) on/off
• Built-in analog circuits :
Two 8-bit A/D converters (main and sub-picture signals)
Two 8-bit D/A converters (Y and C sub-picture signals)
Sync-tip-clump, VCXO, Analog switch ... etc.
• I2C BUS control (parallel/serial control) :
PIP on/off , Sub-picture size(1/9 or 1/16), Frame on/off
(programmable luma level), PIP position (4 corners fixed
position), Picture freeze , Y delay adjustment, Chroma level, Tint,
Black level, Contrast ... etc.
APPLICATION
NTSC color TV
RECOMMENDED OPERATING CONDITION
Supply voltage range........................................................3.1 to 3.5V
Operating frequency.........................................................14.32 MHz
Operating temperature....................................................-20 to 75°C
Input voltage (CMOS interface) "H"........................VDD×0.7 to VDD V
"L".............................0 to VDD×0.3V
Output current (output buffer)........................................±4mA (MAX)
Output load capacitance............................................20pF (MAX) ∗1
Circuit current.........................................................................160mA
NOTICE: Connect a 0.1µF or larger capacitor between VDD and VSS
pins.
∗1 : Include pin capacitance (7pF)
PIN CONFIGURATION (TOP VIEW)
AVss3 (vcxo) 1
VCXO out 2
VCXO in 3
FILTER 4
BIAS 5
AVdd3 (vcxo) 6
AVdd2 (m) 7
Vin (m) 8
Vrt (m) 9
Vrb (m) 10
AVss2 (m) 11
AVdd1 (s) 12
Vin (s) 13
Vrt (s) 14
Vrb (s) 15
AVss1 (s) 16
RESET 17
DVss1 18
DVdd1 19
BGP(s)/TEST0 20
SCK 21
CSYNC(s)/TEST1 22
ACK 23
DATA 24
CLK 25
DVss2 (ram) 26
52 AVssf (ana)
51 Cin
50 TESTEN
49 Yin
48 TEST9
47 Y-PIP
46 TEST8
45 C-PIP
44 AVdd4 (da)
43 C-PIPin
42 AVss4 (da)
41 Y-PIPin
40 ADJ-Ysub
39 Yout-sub
38 ADJ-Csub
37 Cout-sub
36 DVss3
35 DVdd3
34 LOCK/TEST7
33 VD/CSYNC/TEST6
32 HD/TEST5
31 SWM/TEST4
30 MCK
29 fsc/TEST3
28 BGP(m)/TEST2
27 DVdd2 (ram)
Outline 52P4B
1
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI ICs (TV)
M65667SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
BLOCK DIAGRAM
SCK
CSYNC(s)
/TEST1
BGP(s)
/TEST0
Yin
Cin
Vdd / Vss
for test
DATA
CLK
ACK
Vin(s)
Vrt(m)
Vrb(m)
ADJ-Ysub
Yout-sub
Cout-sub
ADJ-Csub
Vin(m)
Vrt(m)
Vrb(m)
Sync tip
Clamp
15
3
3 I2C
I/F
Bias
Sync tip
Clamp
2
A/D
8bit
V-chip
data slicer
Y/C SEP
(LPF,BPF)
Y
Luma
Clamp
Sync
Sep
HD Phase
Select
( I2C )
HPLL 4fsc
C
Demod
Delay
Y6
AFC
Tint
Timing Gen
(Decode)
B-Y 6
R-Y 6
D/A
8bit
Delay
Delay
Delay
6Y
MIX 6 B-Y
D/A
8bit
fsc
LPF
&MPY
6 R-Y
RAM(1H)
Vert-filter
&
MUX
Y
B-Y
R-Y
RAM
96Kbits
Bias
2
A/D
8bit
Level
Detect
Burst Data
Sampling
Phase
Detect
Lock/Free-run
via I2C
VCXO
Driver
Y- PIP
C- PIP
Bias C- PIPin
Back Porch
Clamp
Y- PIPin
SWMG
/TEST7
Timing Gen
(Memory
Cont)
4fsc
VCXO
VD
/CSYNC
/TEST6
HD
/TEST5
FILTER
BIAS
VCXO in
VCXO out
RESET
MCK
BGP(m)
/TEST2
fsc
/TEST3
SWM
/TEST4
2
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