MC12206DT 반도체 회로 부품 판매점
MECL PLL COMPONENTS Serial Input PLL Frequency Synthesizer
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 Motorola Semiconductors |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Serial Input PLL Frequency
Synthesizer
The MC12206 is a 2.0GHz Bipolar monolithic serial input phase locked
loop (PLL) synthesizer with pulse–swallow function. It is designed to
provide the high frequency local oscillator signal of an RF transceiver in
handheld communication applications.
Motorola’s advanced Bipolar MOSAIC™ V technology is utilized for
low power operation at a minimum supply voltage of 2.7V. The device is
designed for operation over 2.7 to 5.5V supply range for input frequencies
up to 2.0GHz with a typical current drain of 7.4mA. The low power
consumption makes the MC12206 ideal for handheld battery operated
applications such as cellular or cordless telephones, wireless LAN or
personal communication services. A dual modulus prescaler is integrated
to provide either a 64/65 or 128/129 divide ratio.
For additional applications information, two InterActiveApNote™
documents containing software (based on a Microsoft Excel
spreadsheet) and an Application Note are available. Please order
DK305/D and DK306/D from the Motorola Literature Distribution Center.
• Low Power Supply Current of 6.7mA Typical for ICC and 0.7mA Typical
for IP
• Supply Voltage of 2.7 to 5.5V
• Dual Modulus Prescaler With Selectable Divide Ratios of 64/65 or
128/129
• On–Chip Reference Oscillator/Buffer
• Programmable Reference Divider Consisting of a Binary 14–Bit
Programmable Reference Counter
• Programmable Divider Consisting of a Binary 7–Bit Swallow Counter
and an 11–Bit Programmable Counter
• Phase/Frequency Detector With Phase Conversion Function
• Balanced Charge Pump Outputs
• Dual Internal Charge Pumps for Bypassing the First Stage of the Loop
Filter to Decrease Lock Time
• Outputs for External Charge Pump
• Operating Temperature Range of –40°C to +85°C
• Space Efficient Plastic Surface Mount SOIC or TSSOP Packages
MC12206
MECL PLL COMPONENTS
Serial Input PLL
Frequency Synthesizer
16
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
20
1
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–03
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
VP
Tstg
Power Supply Voltage, Pin 4 (Pin 5 in 20–lead package)
Power Supply Voltage, Pin 3 (Pin 4 in 20–lead package)
Storage Temperature Range
–0.5 to +6.0
VCC to +6.0
–65 to +150
VDC
VDC
°C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
MOSAIC V, Mfax and InterActiveApNote are trademarks of Motorola, Inc.
1/97
© Motorola, Inc. 1997
1
REV 3
MC12206
φR φP fOUT BISW FC LE DATA CLK
16 15 14 13 12 11 10 9
Pinout: 16–Lead Package (Top View)
1 23 45 6 7
OSCin OSCout VP VCC Do GND LD
8
fIN
φR NC φP fOUT BISW FC LE DATA NC CLK
20 19 18 17 16 15 14 13 12 11
Pinout: 20–Lead Package (Top View)
PIN NAMES
Pin
OSCin
I/O
I
OSCout
VP
VCC
Do
GND
LD
fIN
CLK
DATA
LE
O
—
—
O
—
O
I
I
I
I
FC
BISW
fOUT
φP
φR
NC
I
O
O
O
O
—
1 2 3 4 5 6 7 8 9 10
OSCin NC OSCout VP VCC Do GND LD NC fIN
Function
Oscillator input. A crystal is connected between OSCin and OSCout. An external
source can be AC coupled into this input
Oscillator output. Pin should be left open if external source is used
Power supply for charge pumps (VP should be greater than or equal to VCC) VP
provides power to the Do, BISW and φP outputs
Power supply voltage input. Bypass capacitors should be placed as close as
possible to this pin and be connected directly to the ground plane.
Internal charge pump output. Do remains on at all times
Ground
Lock detect, phase comparator output
Prescaler input. The VCO signal is AC–coupled into this pin
Clock input. Rising edge of the clock shifts data into the shift registers
Binary serial data input
Load enable input (with internal pull up resistor). When LE is HIGH or OPEN, data
stored in the shift register is transferred into the appropriate latch (depending on
the level of control bit). Also, when LE is HIGH or OPEN, the output of the second
internal charge pump is connected to the BISW pin
Phase control select (with internal pull up resistor). When FC is LOW, the
characteristics of the phase comparator and charge pump are reversed. FC also
selects fp or fr on the fOUT pin
Analog switch output. When LE is HIGH or OPEN (“analog switch is ON”) the
output of the second charge pump is connected to the BISW pin. When LE is LOW,
BISW is high impedance
Phase comparator input signal. When FC is HIGH, fOUT=fr, programmable
reference divider output; when FC is LOW, fOUT=fp, programmable divider output
Output for external charge pump. Standard CMOS output level
Output for external charge pump. Standard CMOS output level
No connect
16–Lead Pkg
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
—
20–Lead Pkg
Pin No.
1
3
4
5
6
7
8
10
11
13
14
15
16
17
18
20
2, 9, 12, 19
MOTOROLA
2 HIPERCOMM
BR1334 — Rev 4
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MC12206D
MECL PLL COMPONENTS Serial Input PLL Frequency Synthesizer - Motorola Semiconductors
MC12206DT
MECL PLL COMPONENTS Serial Input PLL Frequency Synthesizer - Motorola Semiconductors