MC10162FN 반도체 회로 부품 판매점
Binary to 1-8 Decoder(High)
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 Motorola Semiconductors |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Binary to 1-8 Decoder (High)
The MC10162 is designed to convert three lines of input data to a
one–of–eight output. The selected output will be high while all other outputs are
low. The enable inputs, when either or both are high, force all outputs low.
The MC10162 is a true parallel decoder. No series gating is used internally,
eliminating unequal delay times found in other decoders.
This device is ideally suited for demultiplexer applications. One of the two
enable inputs is used as the data input, while the other is used as a data enable
input.
A complete mux/demux operation on 16 bits for data distribution is illustrated
in Figure 1 of the MC10161 data sheet.
PD = 315 ns typ/pkg (No Load)
tpd = 4.0 ns typ
tr, tf = 2.0 ns typ (20%–80%)
E0 2
E1 15
A7
B9
C 14
LOGIC DIAGRAM
6 Q0
5 Q1
4 Q2
3 Q3
13 Q4
12 Q5
11 Q6
10 Q7
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
INPUTS
TRUTH TABLE
OUTPUTS
E0 E1 C B A Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
L L LLL H L L L L L L L
L L L LH L H L L L L L L
L L LHL L L H L L L L L
L L L HH L L L H L L L L
L L HLL L L L L H L L L
L L HLH L L L L L H L L
L L HHL L L L L L L H L
L L HHH L L L L L L L H
H X XXX L L L L L L L L
X H XXX L L L L L L L L
MC10162
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
DIP
PIN ASSIGNMENT
VCC1
E0
Q3
Q2
Q1
Q0
A
VEE
1
2
3
4
5
6
7
8
16 VCC2
15 E1
14 C
13 Q4
12 Q5
11 Q6
10 Q7
9B
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
3/93
© Motorola, Inc. 1996
3–78
REV 5
MC10162
ELECTRICAL CHARACTERISTICS
Characteristic
Power Supply Drain Current
Input Current
Output Voltage
Output Voltage
Logic 1
Logic 0
Symbol
IE
IinH
IinL
VOH
VOL
Threshold Voltage
Threshold Voltage
Logic 1
Logic 0
VOHA
VOLA
Switching Times (50Ω Load)
Propagation Delay
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
t14+13–
t14–13+
t13+
t13–
Pin
Under
Test
8
14
14
13
13
13
13
13
13
13
13
13
13
–30°C
Min Max
84
350
0.5
–1.060 –0.890
–1.890 –1.675
–1.890 –1.675
–1.080
–1.655
–1.655
1.5 6.2
1.5 6.2
1.0 3.3
1.0 3.3
Test Limits
+25°C
Min Typ Max
61 76
220
0.5
–0.960
–0.810
–1.850
–1.850
–1.650
–1.650
–0.980
–1.630
–1.630
1.5 4.0 6.0
1.5 4.0 6.0
1.1 2.0 3.3
1.1 2.0 3.3
+85°C
Min Max
84
220
0.3
–0.890 –0.700
–1.825 –1.615
–1.825 –1.615
–0.910
–1.595
–1.595
1.5 6.4
1.5 6.4
1.1 3.5
1.1 3.5
Unit
mAdc
µAdc
µAdc
Vdc
Vdc
Vdc
Vdc
ns
ELECTRICAL CHARACTERISTICS (continued)
@ Test Temperature
–30°C
+25°C
+85°C
Characteristic
Symbol
Pin
Under
Test
Power Supply Drain Current
Input Current
Output Voltage
Output Voltage
Logic 1
Logic 0
IE
IinH
IinL
VOH
VOL
8
14
14
13
13
13
Threshold Voltage
Threshold Voltage
Logic 1
Logic 0
VOHA
VOLA
13
13
13
Switching Times
(50Ω Load)
Propagation Delay
Rise Time
(20 to 80%)
t14+13+
t14–13–
t+
13
13
13
Fall Time
(20 to 80%)
t–
13
VIHmax
–0.890
–0.810
–0.700
TEST VOLTAGE VALUES (Volts)
VILmin
–1.890
VIHAmin VILAmax
–1.205
–1.500
–1.850
–1.105
–1.475
–1.825
–1.035
–1.440
VEE
–5.2
–5.2
–5.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
14
14
2
15
VILmin
14
VIHAmin VILAmax
14
2
15
Pulse In
14
14
14
14
Pulse Out
13
13
13
13
VEE
8
8
8
8
8
8
8
8
8
–3.2 V
8
8
8
8
(VCC)
Gnd
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,16
+2.0 V
1,16
1,16
1,16
1,16
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECL Data
DL122 — Rev 6
3–79
MOTOROLA
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