MC10136FN 반도체 회로 부품 판매점
Universal Hexadecimal Counter
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 Motorola Semiconductors |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Universal Hexadecimal
Counter
The MC10136 is a high speed synchronous counter that can count up, count
down, preset, or stop count at frequencies exceeding 100 MHz. The flexibility of
this device allows the designer to use one basic counter for most applications,
and the synchronous count feature makes the MC10136 suitable for either
computers or instrumentation.
Three control lines (S1, S2, and Carry In) determine the operation mode of
the counter. Lines S1 and S2 determine one of four operations; preset
(program), increment (count up), decrement (count down), or hold (stop count).
Note that in the preset mode a clock pulse is necessary to load the counter, and
the information present on the data inputs (D0, D1, D2, and D3) will be entered
into the counter. Carry Out goes low on the terminal count, or when the counter
is being preset.
This device is not designed for use with gated clocks. Control is via S1 and
S2.
MC10136
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
PD = 625 mW typ/pkg (No Load)
fcount = 150 MHz typ
tpd = 3.3 ns typ (C-Q)
7.0 ns typ (C-Cout)
5.0 ns typ (Cin-Cout)
FUNCTION TABLE
Cin S1 S2
Operating Mode
X L L Preset (Program)
L L H Increment (Count Up)
H L H Hold Count
L H L Decrement (Count Down)
H H L Hold Count
X H H Hold (Stop Count)
DIP
PIN ASSIGNMENT
VCC1
Q2
Q3
Cout
D3
D2
S2
VEE
1
2
3
4
5
6
7
8
16 VCC2
15 Q1
14 Q0
13 CLOCK
12 D0
11 D1
10 Cin
9 S1
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
3/93
© Motorola, Inc. 1996
3–27
REV 5
MC10136
S1 9
S2 7
Carry In
10
LOGIC DIAGRAM
Clock
13
Q0
T
Q0
TC
T Q1
T Q1
TC
T Q2
T
T Q2
TC
T Q3
T
T Q3
TT C
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
12 D0
14 Q0 11 D1
15 Q1
6 D2
2 Q2
5 D3
NOTE: Flip-flops will toggle when all T inputs are low.
3 Q3
4 Carry Out
SEQUENTIAL TRUTH TABLE*
INPUTS
OUTPUTS
Carry Clock
S1 S2 D0 D1 D2 D3 In
** Q0 Q1 Q2 Q3
L LL LHH
L HX XX X
L HX XX X
L HX XX X
X
L
L
L
H L LHH
H H LHH
H L HH H
H H HH H
L HX XX X
L HX XX X
HHX XX X
L LHHL L
H
H
X
X
L H HH H
H H HH H
H H HH H
H HHL L
H LX XX X
H LX XX X
H LX XX X
H LX XX X
L
L
L
L
H L HL L
H HLL L
H L LL L
H H HH H
* Truth table shows logic states assuming inputs vary in sequence shown from top to bottom.
** A clock H is defined as a clock input transition from a low to a high logic level.
Carry
Out
L
H
H
L
H
H
H
L
H
H
L
H
MOTOROLA
3–28
MECL Data
DL122 — Rev 6
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MC10136FN data
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