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Toshiba |
TC74VHC138F/FN/FT/FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHC138F,TC74VHC138FN,TC74VHC138FT,TC74VHC138FK
3-to-8 Line Decoder
The TC74VHC138 is an advanced high speed CMOS 3-to-8
DECODER fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
When the device is enabled, 3 Binary Select inputs (A, B and
C) determine which one of the outputs ( Y0 - Y7 ) will go low.
When enable input G1 is held low or either G2A or G2B is held
high, decoding function is inhibited and all outputs go high.
G1, G2A , and G2B inputs are provided to ease cascade
connection and for use as an address decoder for memory
systems.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
Features
• High speed: tpd = 5.7 ns (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Power down protection is provided on all inputs.
• Balanced propagation delays: tpLH ∼− tpHL
• Wide operating voltage range: VCC (opr) = 2 V to 5.5 V
• Pin and function compatible with 74ALS138
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74VHC138F
TC74VHC138FN
TC74VHC138FT
TC74VHC138FK
Weight
SOP16-P-300-1.27A
SOL16-P-150-1.27
TSSOP16-P-0044-0.65A
VSSOP16-P-0030-0.50
: 0.18 g (typ.)
: 0.13 g (typ.)
: 0.06 g (typ.)
: 0.02 g (typ.)
1 2007-10-01
Pin Assignment
TC74VHC138F/FN/FT/FK
A1
B2
C3
G2A 4
G2B 5
G1 6
Y7 7
GND 8
(top view)
16 VCC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
IEC Logic Symbol
A (1)
B (2)
C (3)
G1
G2A
G2B
(6)
(4)
(5)
BIN/OCT
10
21
42
3
&4
5
EN 6
7
(15) Y0
(14) Y1
(13) Y2
(12) Y3
(11) Y4
(10) Y5
(9) Y6
(7) Y7
A (1)
B (2)
C (3)
G1
G2A
G2B
(6)
(4)
(5)
DMUX
00
2
G
0
7
1
2
3
&4
5
6
7
(15) Y0
(14) Y1
(13) Y2
(12) Y3
(11) Y4
(10) Y5
(9) Y6
(7) Y7
Truth Table
Inputs
Enable
G1 G2A G2B C
LXXX
XHXX
XXHX
HL L L
HL L L
HL L L
HL L L
HL LH
HL LH
HL LH
HL LH
Select
B
X
X
X
L
L
H
H
L
L
H
H
A
X
X
X
L
H
L
H
L
H
L
H
X: Don’t care
Outputs
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
HHHHHHHH
HHHHHHHH
HHHHHHHH
L HHHHHHH
H L HHHHHH
HH L HHHHH
HHH L HHHH
HHHH L HHH
HHHHH L HH
HHHHHH L H
HHHHHHH L
Selected
Output
None
None
None
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
2 2007-10-01
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