W166 판매점 - Spread Spectrum Frequency Timing Generator

W166 반도체 회로 부품 판매점

Spread Spectrum Frequency Timing Generator

Cypress Semiconductor

W166

Spread Spectrum Frequency Timing Generator

Features

• Maximized EMI suppression using Cypress’s Spread

Spectrum technology

• Generates a spread spectrum copy of the provided

input

• Selectable spreading characteristics

• Integrated loop filter components

• Operates with a 3.3V or 5V supply

• SSON# pin enables frequency spreading

• Low power CMOS design

• Available in 8-pin SOIC (Small Outline Integrated

Circuit)

Overview

The W166 incorporates the latest advances in PLL spread

spectrum frequency synthesizer techniques. By frequency

modulating the output with a low-frequency carrier, peak EMI

is greatly reduced. Use of this technology allows systems to

pass increasingly difficult EMI testing without resorting to cost-

ly shielding or redesign.

In a system, not only is EMI reduced in the various clock lines,

but also in all signals which are synchronized to the clock.

Therefore, the benefits of using this technology increase with

the number of address and data lines in the system. The Sim-

plified Block Diagram shows a simple implementation.

Table 1. Frequency Spread Selection

W166

FS1 FS0

Input

Frequency

(MHz)

Output

Frequency (MHz)

50 to 65

fIN ±0.625%

fIN ±1.25%

fIN ±2.5%

fIN –3.75%

Simplified Block Diagram

3.3V or 5V

Oscillator or Reference

Input

W166

Spread Spectrum

Output

(EMI suppressed)

Pin Configuration

CLKIN

GND

FS1

8 SSON#

7 CLKOUT

6 FS0

5 VDD

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

December 20, 1999, rev. **

W166

Pin Definitions

Pin Name

CLKOUT

Pin No.

CLKIN

SSON#

FS0:1

6, 4

VDD

GND

Type

Pin Description

Output Modulated Frequency: Frequency modulated copy of the reference input

(SSON# asserted).

External Reference Frequency Input: Clock input.

No Connect: This pin must be left unconnected.

Spread Spectrum Control (Active LOW): Asserting this signal (active LOW) turns the

internal modulation waveform on. This pin has an internal pull-down resistor.

Frequency Selection Bits 0,1: These pins select the frequency spreading characteris-

tics. Refer to Table 1. These pins have internal pull-up resistors.

Power Connection: Connected to 3.3V or 5V power supply.

Ground Connection: This should be connected to the common ground plane.

Functional Description

The W166 uses a Phase-Locked Loop (PLL) to frequency

modulate an input clock. The result is an output clock whose

frequency is slowly swept over a narrow band near the input

signal. The basic circuit topology is shown in Figure 1. The

input reference signal is divided by Q and fed to the phase

detector. A signal from the VCO is divided by P and fed back

to the phase detector also. The PLL will force the frequency of

the VCO output signal to change until the divided output signal

and the divided reference signal match at the phase detector

input. The output frequency is then equal to the ratio of P/Q

times the reference frequency. (Note: For the W166 the output

frequency is equal to the input frequency.) The unique feature

of the Spread Spectrum Frequency Timing Generator is that a

modulating waveform is superimposed at the input to the VCO.

This causes the VCO output to be slowly swept across a pre-

determined frequency band.

Because the modulating frequency is typically 1000 times

slower than the fundamental clock, the spread spectrum pro-

cess has little impact on system performance.

Frequency Selection With SSFTG

In Spread Spectrum Frequency Timing Generation, EMI re-

duction depends on the shape, modulation percentage, and

frequency of the modulating waveform. While the shape and

frequency of the modulating waveform are fixed, the modula-

tion percentage may be varied.

A larger spreading percentage improves EMI reduction. How-

ever, large spread percentages may either exceed system

maximum frequency ratings or lower the average frequency to

a point where performance is affected. For these reasons, nar-

row and wide modulation selections are provided.

Clock Input

Reference Input

Freq.

Divider

VDD

Phase

Detector

Charge

Pump

VCO

Post

Dividers

CLKOUT

(EMI suppressed)

Feedback

Divider

Modulating

Waveform

PLL

GND

Figure 1. System Block Diagram

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제조업체: Cypress Semiconductor

( cypress )

W166 data

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국내 전력반도체 판매점

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W166 반도체 회로 부품 판매점

Spread Spectrum Frequency Timing Generator

국내 전력반도체 판매점

일반적인 전자부품 판매점

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