UPA1764 반도체 회로 부품 판매점
SWITCHING DUAL N-CHANNEL POWER MOS FET INDUSTRIAL USE
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 NEC |
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA1764
SWITCHING
DUAL N-CHANNEL POWER MOS FET
INDUSTRIAL USE
DESCRIPTION
The µPA1764 is N-channel MOS Field Effect
Transistor designed for high current switching
applications.
FEATURES
• Dual chip type
• Low On-state Resistance
5 RDS(on)1 = 27 mΩ (TYP.) (VGS = 10 V, ID = 3.5 A)
5 RDS(on)2 = 32 mΩ (TYP.) (VGS = 4.5 V, ID = 3.5 A)
5 RDS(on)3 = 34 mΩ (TYP.) (VGS = 4.0 V, ID = 3.5 A)
• Low input capacitance
5 Ciss = 1300 pF (TYP.)
• Built-in G-S protection diode
• Small and surface mount package (Power SOP8)
ORDERING INFORMATION
PART NUMBER
PACKAGE
PACKAGE DRAWING (Unit : mm)
85
1 : Source 1
2 : Gate 1
7, 8 : Drain 1
3 : Source 2
4 : Gate 2
5, 6 : Drain 2
14
5.37 MAX.
6.0 ±0.3
4.4
0.8
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
0.5 ±0.2
0.10
µPA1764G
Power SOP8
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Drain to Source Voltage
VDSS 60 V
Gate to Source Voltage
VGSS ±20 V
Drain Current (DC)
Drain Current (pulse) Note1
Total Power Dissipation (1 unit) Note2
Total Power Dissipation (2 unit) Note2
ID(DC) ±7 A
ID(pulse)
±28
A
PT 1.7 W
PT 2.0 W
Channel Temperature
Tch 150 °C
Storage Temperature
Single Avalanche Current Note3
5 Single Avalanche Energy Note3
Tstg –55 to +150 °C
IAS 7 A
EAS 98 mJ
EQUIVALENT CIRCUIT
(1/2 circuit)
Drain
Gate
Body
Diode
Gate
Protection
Diode
Source
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1 %
5 2. Mounted on ceramic substrate of 2000 mm2 x 2.2 mm
3. Starting Tch = 25 °C, RG = 25 Ω, VGS = 20 V → 0 V
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. G14329EJ1V0DS00 (1st edition)
Date Published January 2000 NS CP(K)
Printed in Japan
The mark 5 shows major revised points.
© 1999,2000
µ PA1764
5 ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN. TYP. MAX. UNIT
Drain to Source On-state Resistance
RDS(on)1 VGS = 10 V, ID = 3.5 A
27 35 mΩ
RDS(on)2 VGS = 4.5 V, ID = 3.5 A
32 42 mΩ
RDS(on)3 VGS = 4.0 V, ID = 3.5 A
34 46 mΩ
Gate to Source Cut-off Voltage
VGS(off) VDS = 10 V, ID = 1 mA
1.5 2.0 2.5 V
Forward Transfer Admittance
| yfs | VDS = 10 V, ID = 3.5 A
5.0 9.0
S
Drain Leakage Current
IDSS VDS = 60 V, VGS = 0 V
10 µA
Gate to Source Leakage Current
IGSS VGS = ±20 V, VDS = 0 V
±10 µA
Input Capacitance
Ciss VDS = 10 V
1300
pF
Output Capacitance
Coss
VGS = 0 V
230 pF
Reverse Transfer Capacitance
Crss f = 1 MHz
110 pF
Turn-on Delay Time
td(on)
ID = 3.5 A
15 ns
Rise Time
tr VGS(on) = 10 V
69 ns
Turn-off Delay Time
td(off)
VDD = 30 V
65 ns
Fall Time
tf RG = 10 Ω
27 ns
Total Gate Charge
QG ID = 7.0 A
29 nC
Gate to Source Charge
QGS
VDD = 48 V
3.6 nC
Gate to Drain Charge
QGD
VGS = 10 V
7.4 nC
Body Diode Forward Voltage
VF(S-D) IF = 7.0 A, VGS = 0 V
0.84 V
Reverse Recovery Time
trr IF = 7.0 A, VGS = 0 V
40 ns
Reverse Recovery Charge
Qrr di/dt = 100 A / µs
66 nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
PG.
VGS = 20 → 0 V
50 Ω
L
VDD
ID
VDD
IAS BVDSS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 µs
Duty Cycle ≤ 1 %
RL VGS
VGS
Wave Form
10 %
0
VGS(on) 90 %
VDD
ID 90 %
ID 0 10 %
Wave Form
ID
90 %
10 %
td(on) tr td(off) tf
ton toff
2 Data Sheet G14329EJ1V0DS00
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