UPA1552 반도체 회로 부품 판매점
N-CHANNEL POWER MOS FET ARRAY SWITCHING USE
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 NEC |
DATA SHEET
COMPOUND FIELD EFFECT POWER TRANSISTOR
µPA1552B
N-CHANNEL POWER MOS FET ARRAY
SWITCHING USE
DESCRIPTION
The µPA1552B is N-channel Power MOS FET Array
that built in 4 circuits designed, for solenoid, motor and
lamp driver.
PACKAGE DIMENSIONS
in millimeters
26.8 MAX.
4.0
FEATURES
• 4 V driving is possible
• Large Current and Low On-state Resistance
ID(DC) = ±5.0 A
RDS(on)1 ≤ 0.18 Ω MAX. (VGS = 10 V, ID = 3 A)
RDS(on)2 ≤ 0.24 Ω MAX. (VGS = 4 V, ID = 3 A)
• Low Input Capacitance Ciss = 200 pF TYP.
ORDERING INFORMATION
Type Number
µPA1552BH
Package
10 Pin SIP
ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C)
Drain to Source Voltage VDSS Note 1
60
Gate to Source Voltage
VGSS Note 2
±20
Drain Current (DC)
Drain Current (pulse)
Total Power Dissipation
Total Power Dissipation
ID(DC)
ID(pulse) Note 3
PT1 Note 4
PT2 Note 5
±5.0
±20
28
3.5
Channel Temperature
TCH
150
Storage Temperature
Single Avalanche Current
Single Avalanche Energy
Tstg
IAS Note 6
EAS Note 6
–55 to +150
5.0
2.5
V
V
A/unit
A/unit
W
W
˚C
˚C
A
mJ
1.4 0.6±0.1
2.54
1.4
0.5±0.1
1 2 3 4 5 6 7 8 910
CONNECTION DIAGRAM
3579
24 68
1 10
ELECTRODE CONNECTION
2, 4, 6, 8 : Gate
3, 5, 7, 9 : Drain
1, 10 : Source
Notes 1. VGS = 0
3. PW ≤ 10 µs, Duty Cycle ≤ 1 %
5. 4 Circuits, TA = 25 ˚C
2. VDS = 0
4. 4 Circuits, TC = 25 ˚C
6. Starting TCH = 25 ˚C, V DD = 30 V, VGS = 20 V → 0,
RG = 25 Ω, L = 100 µH
The diode connected between the gate and source of the transistor serves as a protector against ESD. When this
device is actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage
may be applied to this device.
Document No. G10599EJ2V0DS00 (2nd edition)
Date Published December 1995 P
Printed in Japan
© 1995
µPA1552B
ELECTRICAL CHARACTERISTICS (TA = 25 ˚C)
CHARACTERISTIC
Drain Leakage Current
Gate Leakage Current
Gate Cutoff Voltage
Forward Transfer Admittance
Drain to Source On-State
Resistance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
SYMBOL
IDSS
IGSS
VGS(off)
| Yfs |
RDS(on)1
RDS(on)2
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QG
QGS
QGD
VF(S-D)
trr
Qrr
TEST CONDITIONS
VDS = 60 V, VGS = 0
VGS = ±20 V, VDS = 0
VDS = 10 V, ID = 1.0 mA
VDS = 10 V, ID = 3.0 A
VGS = 10 V, ID = 3.0 A
VGS = 4.0 V, ID = 3.0 A
VDS = 10 V, VGS = 0, f = 1.0 MHz
ID = 3.0 A, VGS = 10 V, VDD ·=· 30 V,
RL = 10 Ω
VGS = 10 V, ID = 5.0 A, VDD = 48 V
IF = 5.0 A, VGS = 0
IF = 5.0 A, VGS = 0, di/dt = 50 A/µs
MIN.
1.0
2.4
TYP.
0.09
0.12
200
150
55
20
100
670
310
13
2
4.7
1.0
280
820
MAX.
10
±10
2.0
0.18
0.24
UNIT
µA
µA
V
S
Ω
Ω
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
Test Circuit 1 Avalanche Capability Test Circuit 2 Switching Time
D.U.T.
RG = 25 Ω
PG
VGS = 20 V → 0
50 Ω
L
VDD
D.U.T.
PG. RG
RG = 10 Ω
VDD
ID
IAS
BVDSS
VDS
Starting TCH
VGS
0
t
t = 1 µs
Duty Cycle ≤ 1 %
Test Circuit 3 Gate Charge
RL
VGS
Wave Form
VDD
ID
Wave Form
VGS
10 %
0
VGS (on)
90 %
ID
0 10 %
td (on)
90 %
ID
tr td (off)
90 %
10 %
tf
ton toff
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
2
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