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UMC Corporation |
UN13750
Programmable
Encoder/Decoder
Single chip contains both Encoder and Decoder.
3V to 11 V operation.
On chip oscillator uses non-critical RC components.
Cross interference of recetver is virtually eliminated
by circuitry which requires 4 valid words to be received,
each within 64ms of the other.
Schmitt Trigger input provides excellent noise immunity.
Applications. alarm control system, security system
cordless telephone, remote control.
Interfaces with RF, ultrasonic, or infrared modulators
and demodulators
I
General Description
T h e U M 3 7 5 0 E n c o d e r / D e c o d e r is a CMOS/LSI digital
code Transmitter-Receiver system. Working in the trans-
mit (encoder) mode, the UM3750 will sequentially encode
and transmit 12 bits of input. Each of the 12 bits may
be 1 or 0 to allow 4096 different codes.
In the receive (decoder) mode, the incoming signal is
compared to the local code In a sequential manner O n c e
an error IS detected the system will reset and beain its
comparison on the next word. If all 12 bits are received
correctly, a “valid” signal is generated. This signal clears a
64ms counter and triggers a 3-stage counter. The 3-stage
counter counts the “valid” pluses and when 4 pulses have
been detected, the TX/RX output pin goes low. After the
TX/RX output pin goes low, the next “valid” must be
received within 128ms, giving a one valid in 6 requirement
to keep the TX/RX output pin.
Pin Configurations
www.DataSheet4U.com
“cc
TX/RX OUTPUT
RECEIVER INPUT
MODE SELECT
“ss
R.C INPUT
A12
All
A10
“cc
TX/RX OUTPUT
RECEIVER INPUT
MODE SELECT
“SS
R.C. INPUT
A12
All
A10
NC
2-3
Block Diagram
R.C.INPUT - - - - - - -
urn3750
CPCLK
RID
II
LCOMPARATOR
ERROR
CLR
MXCLKR
MXD
WD
7i
STATE
CONTROLLER
TIM0
VLD
INIT
64ms/128ms
TIMER
I
VALID 4
COUNTER
Al-Al2
T/R OUT
Block Diagram Description
CPCLK CLK of Comparator
WXCLKR: CLK of Multiplexer when in Receiver mode
WXCLKT CLK of Multiplexer when in Transmitter mode
MXD:
Output data of Multiplexer (one of Al, A2 ....
A12)
wwwR.IDDataSheSeat4mUpl.ecdomdata by Sampling CKT
VLD.
“Valid” signal. It is used to trigger Valid 4
Counter and reset 64ms/128ms Timer
CLR:
ERROR:
TIMO :
T/R OUT:
INIT:
WD:
TXO:
PXO:
Clear signal of Comparator
Error signal from Comparator
TIMER time-out signal (64ms or 128ms)
Transmit/Receiver output pin
Reset signal of Valid 4 Counter
Word detected signal
Transmitter output
Receiver output
2-4
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