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SL74HC221N 반도체 회로 부품 판매점

Dual Monostable Multivibrator



System Logic Semiconductor 로고
System Logic Semiconductor
SL74HC221N 데이터시트, 핀배열, 회로
SL74HC221
Dual Monostable Multivibrator
The SL74HC221 is identical in pinout to the LS/ALS221. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
There are two trigger inputs, A INPUT (negative edge) and
B INPUT (positive edge). These inputs are valid for rising/falling
signals
The device may also be triggered by using the CLR input (positive-
edge) because of the Schmitt-trigger input; after triggering the output
maintains the MONOSTABLE state for the time period determined by
the external resistor RX and capacitor CX. Taking CLR low breaks this
MONOSTABLE STATE. If the next trigger pulse occurs during the
MONOSTABLE period it makes the MONOSTABLE period longer.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 3.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
ORDERING INFORMATION
SL74HC221N Plastic
SL74HC221D SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
PIN 16 =VCC
PIN 8 = GND
Note
(1) CX, RX, DX are external components.
(2) DX is a clamping diode.
The external capacitor is charged to VCC in the stand-by
state, i.e. no trigger. When the supply voltage is turned off
CX is discharged mainly through an internal parasitic diode.
If CX is sufficiently large and VCC decreases rapidy, there will
be some possibility of damaging the I.C. with a surge
current or latch-up. If the voltage supply filter capacitor is
large enough and VCC decrease slowly, the surge current is
automatically limited and damage the I.C. is avoided. The
maximum forward current of the parasitic diode is
approximately 20 mA.
FUNCTION TABLE
Inputs
A B CLR
HH
Outputs
QQ
X L H L* H*
H X H L* H*
LH
LH
XX L
LH
X = don’t care
* - except for monostable period
Note
Output
Enable
Inhibit
Inhibit
Output
Enable
Output
Enable
Inhibit
SLS
System Logic
Semiconductor


SL74HC221N 데이터시트, 핀배열, 회로
SL74HC221
MAXIMUM RATINGS*
Symbol
VCC
VIN
VOUT
IIN
IOUT
ICC
PD
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
A, B, CLR
CX, RX
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Value
-0.5 to +7.0
-1.5 to VCC +1.5
-0.5 to VCC +0.5
±20
±30
±25
±50
750
500
Tstg Storage Temperature
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
-65 to +150
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
Unit
V
V
V
mA
mA
mA
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
TA
tr, tf
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time - CLR
(Figure 2)
A or B
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
Min
3.0 **
0
-55
0
0
0
-
Max
6.0
VCC
+125
1000
500
400
No
Limit
Unit
V
V
°C
ns
RX External Timing Resistor
VCC <4.5 V
VCC 4.5 V
10 1000 k
2.0 1000
CX External Timing Capacitor
0 No µF
Limit
** The SL74HC123 will function at 2.0 V but for optimum pulse width stability, VCC should be above
3.0 V.
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND(VIN or VOUT)VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
SLS
System Logic
Semiconductor




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