USB6B1 반도체 회로 부품 판매점
DATA LINES PROTECTION
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 STMicroelectronics |
®
Application Specific Discretes
A.S.D.
USB6Bx
DATA LINES PROTECTION
APPLICATIONS
Where transient overvoltage protection in sensi-
tive equipment is required, such as:
- Universal Serial Bus ports
- RS-423 interfaces
- RS-485 interfaces
- ISDN equipment
- T1/E1 line cards
- HDSL / ASDL interfaces
FEATURES
n Full diode bridge with integrated clamping protection
n Breakdown voltage : VBR = 6V min.
n Peak pulse power dissipation : PPP = 500W (8/20µs)
n Very low capacitance, compatible with high debit
data or signal rates.
DESCRIPTION
In order to prevent fast transients from leading
to severe damages in a high speed data sys-
tem, a specific protection has been developed
by STMicroelectronics.
The USB6Bx protects the two input lines
against overvoltage. Besides, this device also
keeps the power rails in a safe limit thanks to
the integrated Transil diode.
BENEFITS
n Provides protection for each line and between
the supply voltage and GND : 25A , 8/20µs.
n High ESD protection level : up to level 3 per
MIL STD 883C-Method 3015-6
n Separated inputs and outputs (so-called 4-point
structure) to improve ESD susceptibility.
n Comprehensive package pin-out for immediate
implementation.
COMPLIES WITH THE FOLLOWING STANDARDS:
MIL STD 883C - Method 3015-6
class 3 C = 100 pF R = 1500 Ω
3 positive strikes and 3 negative strikes (F = 1 Hz)
IEC-1000-4-2 level 4
15 kV (air discharge)
8 kV (contact discharge)
SO8
DIL8
FUNCTIONAL DIAGRAM
Vcc
I/01
I/02
GND
TM: ASD and TRANSIL are trademarks of ST Microelectronics.
August 1999 Ed : 5A
Vcc
I/01
I/02
GND
1/9
USB6Bx
TECHNICAL INFORMATION
SURGE PROTECTION
The USB6Bx is particularly optimized to perform
surge protection based on the rail to rail topology.
The clamping voltage VCL can be estimated as follow:
VCL+ =Vcc + VF for positive surges
VCL - = - VF
for negative surges
with: VF = Vt + rd.Ip
(VF forward drop voltage) / (Vt forward drop
threshold voltage)
Note: the estimations do not take into account
phenomena due to parasitic inductances.
Fig. A1 :
ESD
SURGE
Lw
Lw di
Vf dt
I/O
+Vcc
VI/O
Lw di
dt
Vcl+ =
Vcc+Vf+
Lw
di
dt
surge >0
Vcl- =
-Vf-
Lw
di
dt
surge <0
GND
Vcl+
Lw di
dt
Vcc+Vf
POSITIVE
SURGE
tr=1ns
t
tr=1ns
-Vf
-Lw di
dt
NEGATIVE
SURGE
Vcl-
t
2/9
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USB6B1 data
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