X76F100P-3.0 반도체 회로 부품 판매점
1K 128 x 8 Bit
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 Xicor |
1K
X76F100
128 x 8 Bit
Secure SerialFlash
FEATURES
• 64-bit password security
• One array (112-bytes) two passwords (16-bytes)
—Read password
—Write password
• Programmable passwords
• Retry counter register
—Allows 8 tries before clearing of the array
• 32-bit response to reset (rst input)
• 8-byte sector Write Mode
• 1MHz clock rate
• 2-wire serial interface
• Low power CMOS
—3.0 to 5.5V operation
—Standby current less than 1µA
—Active current less than 3 mA
• High reliability endurance:
—100,000 write cycles
• Data retention: 100 years
• Available in:
—8-lead PDIP, SOIC, MSOP, and smart car module
DESCRIPTION
The X76F100 is a Password Access Security Supervi-
sor, containing one 896-bit Secure SerialFlash array.
Access to the memory array can be controlled by two
64-bit passwords. These passwords protect read and
write operations of the memory array.
The X76F100 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA). Access to the
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same bus.
The X76F100 also features a synchronous response
to reset providing an automatic output of a hard-wired
32-bit data stream conforming to the industry standard
for memory cards.
The X76F100 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
BLOCK DIAGRAM
CS
SCL
SDA
Interface
Logic
RST
Chip Enable
Data Transfer
Array Access
Enable
Password Array
and Password
Verification Logic
Reset
Response Register
8K Byte
SerialFlash Array
Array 0
(Password Protected)
32 Byte
SerialFlash Array
Array 1
(Password Protected)
Retry Counter
REV 1.0 6/22/00
www.xicor.com
Characteristics subject to change without notice. 1 of 16
X76F100
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is an open drain serial data input/output pin. Dur-
ing a read cycle, data is shifted out on this pin. During
a write cycle, data is shifted in on this pin. In all other
cases, this pin is in a high impedance state.
Chip Select (CS)
When CS is high, the X76F100 is deselected and the
SDA pin is at high impedance and unless an internal
write operation is underway, the X76F100 will be in
standby mode. CS low enables the X76F100, placing it
in the active mode.
Reset (RST)
RST is a device reset pin. When RST is pulsed high
while CS is low the X76F100 will output 32 bits of fixed
data which conforms to the standard for “synchronous
response to reset”. CS must remain LOW and the part
must not be in a write cycle for the response to reset to
occur. See Figure 7. If at any time during the response
to reset CS goes HIGH, the response to reset will be
aborted and the part will return to the standby state.
The response to reset is “mask programmable” only!
To ensure the correct communication, RST must
remain LOW under all conditions except when running
a “Response to Reset sequence”.
Data is transferred in 8-bit segments, with each trans-
fer being followed by an ACK, generated by the receiv-
ing device.
If the X76F100 is in a nonvolatile write cycle a “no
ACK” (SDA=High) response will be issued in response
to loading of the command byte. If a stop is issued prior
to the nonvolatile write cycle the write operation will be
terminated and the part will reset and enter into a
standby mode.
The basic sequence is illustrated in Figure 1.
PIN NAMES
Symbol
CS
SDA
SCL
RST
VCC
VSS
NC
Description
Chip Select Input
Serial Data Input/Output
Serial Clock Input
Reset Input
Supply Voltage
Ground
No Connect
PIN CONFIGURATION
DEVICE OPERATION
The X76F100 memory array consists of fourteen
8-byte sectors. Read or write access to the array
always begins at the first address of the sector. Read
operations then can continue indefinitely. Write opera-
tions must total 8-bytes.
There are two primary modes of operation for the
X76F100; Protected READ and protected WRITE. Pro-
tected operations must be performed with one of two 8-
byte passwords.
The basic method of communication for the device is
established by first enabling the device (CS LOW),
generating a start condition, then transmitting a com-
mand, followed by the correct password. All parts will
be shipped from the factory with all passwords equal to
‘0’. The user must perform ACK Polling to determine
the validity of the password, before starting a data
transfer (see Acknowledge Polling.) Only after the cor-
rect password is accepted and a ACK polling has been
performed, can the data transfer occur.
VCC
NC
NC
VSS
VSS
CS
SDA
NC
PDIP
18
27
36
45
SOIC
18
27
36
45
RST
SCL
SDA
CS
VCC
RST
SCL
NC
VSS
NC
CS
SDA
MSOP
18
27
36
45
VCC
NC
RST
SCL
Smart Card
VCC
RST
SCL
NC
GND
CS
SDA
NC
REV 1.0 6/22/00
www.xicor.com
Characteristics subject to change without notice. 2 of 16
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제조업체: Xicor
( xicor )
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