X25166V14I 판매점 - Programmable Watchdog Timer w/Serial E 2 PROM

X25166V14I 반도체 회로 부품 판매점

Programmable Watchdog Timer w/Serial E 2 PROM

Xicor

64K

X25644/46

8K x 8 Bit

32K

X25324/26

4K x 8 Bit

16K

X25164/66

2K x 8 Bit

Programmable Watchdog Timer w/Serial E2PROM

FEATURES

• Programmable Watchdog Timer with Reset

Assertion

—Reset Signal Valid to Vcc=1V

—Power Up Reset Control

• Save Critical Data With Block LockTM Protection

—Block LockTM Protect 0, 1/4, 1/2 or all of

Serial E2PROM Memory Array

• In Circuit Programmable ROM Mode

• Long Battery Life With Low Power Consumption

—<50µA Max Standby Current, Watchdog On

—<1µA Max Standby Current, Watchdog Off

—<5mA Max Active Current during Write

—<400µA Max Active Current during Read

• 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power

Supply Operation

• 2MHz Clock Rate

• Minimize Programming Time

—32 Byte Page Write Mode

—Self-Timed Write Cycle

—5ms Write Cycle Time (Typical)

• SPI Modes (0,0 & 1,1)

• Built-in Inadvertent Write Protection

—Power-Up/Power-Down Protection Circuitry

—Write Enable Latch

—Write Protect Pin

• High Reliability

• Available Packages

—14-Lead SOIC (X2564x)

—14-Lead TSSOP (X2532x, X2516x)

—8-Lead SOIC (X2532x, X2516x)

BLOCK DIAGRAM

SCK

RESET/RESET

DATA

COMMAND

DECODE &

CONTROL

LOGIC

RESET

CONTROL

DESCRIPTION

These devices combine two popular functions, Watchdog

Timer, and Serial E2PROM Memory in one package. This

combination lowers system cost, reduces board space

requirements, and increases reliability.

The Watchdog Timer provides an independent protection

mechanism for microcontrollers. During a system failure,

the device will respond with a RESET/RESET signal

after a selectable time-out interval. The user selects the

interval from three preset values. Once selected, the

interval does not change, even after cycling the power.

The memory portion of the device is a CMOS Serial

E2PROM array with Xicor’s Block LockTM Protection. The

array is internally organized as x 8. The device features a

Serial Peripheral Interface (SPI) and software protocol

allowing operation on a simple four-wire bus.

The device utilizes Xicor’s proprietary Direct WriteTM cell,

providing a minimum endurance of 100,000 cycles per

sector and a minimum data retention of 100 years.

X - DECODE

LOGIC

STATUS

PAGE DECODE LOGIC

32 8

SERIAL

E2PROM

ARRAY

WATCHDOG

TIMER

WRITE,

WP BLOCK LOCK &

ICP ROM CONTROL

©Xicor, Inc. 1994, 1995, 1996 Patents Pending

7050 -1.0 6/20/97 T0/C0/D0 SH

HIGH

VOLTAGE

CONTROL

7029 FRM 01

Characteristics subject to change without notice

X25644/46

X25324/26

X25164/66

PIN DESCRIPTIONS

Serial Output (SO)

SO is a push/pull serial data output pin. During a read

cycle, data is shifted out on this pin. Data is clocked out by

the falling edge of the serial clock.

Serial Input (SI)

SI is a serial data input pin. All opcodes, byte addresses,

and data to be written to the memory are input on this pin.

Data is latched by the rising edge of the serial clock.

Serial Clock (SCK)

The Serial Clock controls the serial bus timing for data

input and output. Opcodes, addresses, or data present on

the SI pin are latched on the rising edge of the clock input,

while data on the SO pin change after the falling edge of

the clock input.

Chip Select (CS)

When CS is HIGH, the device is deselected and the SO

output pin is at high impedance and unless a nonvolatile

write cycle is underway, the device will be in the standby

power mode. CS LOW enables the device’s, placing it in

the active power mode. It should be noted that after

power-up, a HIGH to LOW transition on CS is required

prior to the start of any operation.

Write Protect (WP)

When WP is low and the nonvolatile bit WPEN is “1”,

nonvolatile writes to the device’s Status Register are

disabled, but the part otherwise functions normally. When

WP is held high, all functions, including nonvolatile writes

to the Status Register operate normally. If an internal

Status Register Write Cycle has already been initiated,

WP going low while WPEN is a “1” will have no effect on

this write. Subsequent write attempts to the Status

The WP pin function is blocked when the WPEN bit in the

Status Register is “0”. This allows the user to install the

device in a system with WP pin grounded and still be able

to program the Status Register. The WP pin functions will

be enabled when the WPEN bit is set to a “1”.

Reset (RESET/RESET)

RESET/RESET is an active LOW/HIGH, open drain out-

put which goes active whenever the Watchdog Timer is

enabled and CS remains either HIGH or LOW longer than

the selectable Watchdog time-out period. It will remain

active for tRST, the Reset Timeout period. A falling edge of

CS will reset the Watchdog Timer.

PIN CONFIGURATION

0.345” SO

VSS

14-LEAD SOIC

1 14

2 13

3 12

X25644/46

4 11

5 10

0.244”

Not to Scale

V CC

RESET/RESET

SCK

0.197” WP

VSS

8-LEAD SOIC

2 X25324/26 7

X25164/66

0.244”

V CC

RESET/RESET

SCK

14-LEAD TSSOP

0.200” NC

VSS

1 14

2 13

3 X25324/28 12

4 X25164/66 11

5 10

0.177”

V CC

RESET/RESET

SCK

7036 FRM 02

PIN NAMES

Symbol

Description

CS Chip Select Input

SO Serial Output

SI Serial Input

SCK

Serial Clock Input

VSS

VCC

RESET/RESET

Write Protect Input

Ground

Supply Voltage

Reset Output

7029 FRM T01

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( xicor )

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X25166V14I 반도체 회로 부품 판매점

Programmable Watchdog Timer w/Serial E 2 PROM

국내 전력반도체 판매점

일반적인 전자부품 판매점

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