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Samsung semiconductor |
S524AD0XD1/D0XF1
128K/256K-bit
Serial EEPROM
for Low Power
Data Sheet
OVERVIEW
The S524AD0XD1/D0XF1 serial EEPROM has a 128K/256K-bit (16,384/32,768 bytes) capacity, supporting the
standard I2C™-bus serial interface. It is fabricated using Samsung’s most advanced CMOS technology. It has
been developed for low power and low voltage applications (1.8 V to 5.5 V). One of its major feature is a
hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled
by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 64 bytes of data into
the EEPROM in a single write operation. Another significant feature of the S524AD0XD1/D0XF1 is its support for
fast mode and standard mode.
FEATURES
I2C-Bus Interface
• Two-wire serial interface
• Automatic word address increment
EEPROM
• 128K/256K-bit (16,384/32,768 bytes) storage
area
• 64-byte page buffer
• Typical 3 ms write cycle time with
auto-erase function
• Hardware-based write protection for the entire
EEPROM (using the WP pin)
• EEPROM programming voltage generated
on chip
• 500,000 erase/write cycles
• 50 years data retention
Operating Characteristics
• Operating voltage
— 1.8 V to 5.5 V
• Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 400 µA at 5.5 V
— Maximum stand-by current: < 1 µA at 5.5 V
• Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (industrial)
• Operating clock frequencies
— 400 kHz at standard mode
— 1 MHz at fast mode
• Electrostatic discharge (ESD)
— 5,000 V (HBM)
— 500 V (MM)
Packages
• 8-pin DIP, and TSSOP
8-1
S524AD0XD1/D0XF1 SERIAL EEPROM
DATA SHEET
SDA
WP
SCL
A0
A1
A2
Start/Stop
Logic
Slave Address
Comparator
Control Logic
Word Address
Pointer
HV Generation
Timing Control
Row
decoder
EEPROM
Cell Array
16,384 x 8 bits
32,768 x 8 bits
DOUT and ACK
Column Decoder
Data Register
Figure 8-1. S524AD0XD1/D0XF1 Block Diagram
8-2
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