ispLSI1016EA-100LT44 판매점 - In-System Programmable High Density PLD

ispLSI1016EA-100LT44 반도체 회로 부품 판매점

In-System Programmable High Density PLD

Lattice Semiconductor

ispLSI® 1016EA

In-System Programmable High Density PLD

Features

Functional Block Diagram

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 2000 PLD Gates

— 32 I/O Pins, One Dedicated Input

— 96 Registers

— High-Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— Functionally Compatible with ispLSI 1016E

• NEW FEATURES

— 100% IEEE 1149.1 Boundary Scan Testable

— ispJTAG™ In-System Programmable via IEEE 1149.1

(JTAG) Test Access Port

— User-Selectable 3.3V or 5V I/O Supports Mixed-

Voltage Systems (VCCIO Pin)

— Open-Drain Output Option

• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY

— fmax = 200 MHz Maximum Operating Frequency

— tpd = 4.5 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Device for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

A1 D Q

A2 D Q

Logic

A3 Array D Q GLB

A7 Global Routing Pool (GRP)

CLK

Description

0139C/1016EA

The ispLSI 1016EA is a High Density Programmable

Logic Device containing 96 Registers, 32 Universal I/O

pins, one Dedicated Input pin, two Dedicated Clock Input

pins, one Global OE input pin and a Global Routing Pool

(GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 1016EA fea-

tures 5V in-system programmability (ISP™) and in-system

diagnostic capabilities via an IEEE 1149.1 Test Access

Port. The ispLSI 1016EA offers non-volatile

reprogrammability of the logic, as well as the intercon-

nect to provide truly reconfigurable systems. A functional

superset of the ispLSI 1016 architecture, the ispLSI

1016EA device adds user-selectable 3.3V or 5V I/O and

open-drain output options.

The basic unit of logic on the ispLSI 1016EA device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1...B7 (Figure 1). There are a total of 16 GLBs in the

ispLSI 1016EA device. Each GLB has 18 inputs, a

programmable AND/OR/Exclusive OR array, and four

outputs which can be configured to be either combinato-

rial or registered. Inputs to the GLB come from the GRP

and a dedicated input. All of the GLB outputs are brought

back into the GRP so that they can be connected to the

inputs of any other GLB on the device.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

June 2000

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

1016ea_01

Specifications ispLSI 1016EA

Functional Block Diagram

Figure 1. ispLSI 1016EA Functional Block Diagram

VCCIO

Generic

Logic Blocks

(GLBs)

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

TDI

TDO

TMS

TCK

Megablock

Global

Routing

Pool

(GRP)

*Note: Y1 and RESET are multiplexed on the same pin

GOE 0

I/O 31

I/O 30

I/O 29

B6 I/O 28

B5 I/O 27

I/O 26

I/O 25

B4 I/O 24

B3 I/O 23

I/O 22

I/O 21

B2 I/O 20

B1 I/O 19

I/O 18

I/O 17

B0 I/O 16

Clock

Distribution

Network

CLK 0

CLK 1

CLK 2

IOCLK 0

IOCLK 1

0139/1016EA

The device also has 32 I/O cells, each of which is directly

connected to an I/O pin. Each I/O cell can be individually

programmed to be a combinatorial input, registered

input, latched input, output or bi-directional

I/O pin with 3-state control. The signal levels are TTL

compatible voltages and the output drivers can source

2 mA or sink 8 mA. Each output can be programmed

independently for fast or slow output slew rate to mini-

mize overall output switching noise. By conneting the

VCCIO pin to a common 5V or 3.3V power supply, I/O

output levels can be matched to 5V or 3.3V-compatible

voltages.

Clocks in the ispLSI 1016EA device are selected using

the Clock Distribution Network. Two dedicated clock pins

(Y0 and Y1) are brought into the distribution network, and

five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and

IOCLK 1) are provided to route clocks to the GLBs and

I/O cells. The Clock Distribution Network can also be

driven from a special clock GLB (B0 on the ispLSI

1016EA device). The logic of this GLB allows the user to

create an internal clock from a combination of internal

signals within the device.

Programmable Open-Drain Outputs

Eight GLBs, 16 I/O cells, a dedicated input (if available)

and one ORP are connected together to make a

Megablock (see Figure 1). The outputs of the eight GLBs

are connected to a set of 16 universal I/O cells by the

ORP. Each ispLSI 1016EA device contains two

Megablocks.

The GRP has, as its inputs, the outputs from all of the

GLBs and all of the inputs from the bi-directional I/O cells.

All of these signals are made available to the inputs of the

GLBs. Delays through the GRP have been equalized to

minimize timing skew.

In addition to the standard output configuration, the

outputs of the ispLSI 1016EA are individually program-

mable, either as a standard totem-pole output or an

open-drain output. The totem-pole output drives the

specified Voh and Vol levels, whereas the open-drain

output drives only the specified Vol. The Voh level on the

open-drain output depends on the external loading and

pull-up. This output configuration is controlled by a pro-

grammable fuse. The default configuration when the

device is in bulk erased state is totem-pole configuration.

The open-drain/totem-pole option is selectable through

the ispDesignEXPERT software tools.

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ispLSI1016EA-100LT44 반도체 회로 부품 판매점

In-System Programmable High Density PLD

국내 전력반도체 판매점

일반적인 전자부품 판매점

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