ISPL1048E-100LQI 판매점 - High-Density Programmable Logic

ISPL1048E-100LQI 반도체 회로 부품 판매점

High-Density Programmable Logic

Lattice Semiconductor

ispLSI® 1048E

High-Density Programmable Logic

Features

Functional Block Diagram

• HIGH DENSITY PROGRAMMABLE LOGIC

— 8,000 PLD Gates

— 96 I/O Pins, Twelve Dedicated Inputs

— 288 Registers

— High-Speed Global Interconnects

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— Functionally and Pin-out Compatible to ispLSI 1048C

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY

— fmax = 125 MHz Maximum Operating Frequency

— tpd = 7.5 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Eraseable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

• IN-SYSTEM PROGRAMMABLE

— In-System Programmable (ISP™) 5V Only

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispLSI DEVELOPMENT TOOLS

ispVHDL™ Systems

— VHDL/Verilog-HDL/Schematic Design Options

— Functional/Timing/VHDL Simulation Options

ispDS+™ VHDL Synthesis-Optimized Logic Fitter

— Supports Leading Third-Party Design Environments

for Schematic Capture, Synthesis and Timing

Simulation

— Static Timing Analyzer

ispDS™ Software

— Lattice HDL or Boolean Logic Entry

— Functional Simulator and Waveform Viewer

ISP Daisy Chain Download Software

Output Routing Pool

F7 F6 F5 F4 F3 F2 F1 F0

Output Routing Pool

E7 E6 E5 E4 E3 E2 E1 E0

Global Routing Pool (GRP)

Logic

Array D Q GLB

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

C0 C1 C2 C3 C4 C5 C6 C7

CLK

Output Routing Pool

0139G1A-isp

Description

The ispLSI 1048E is a High-Density Programmable Logic

Device containing 288 Registers, 96 Universal I/O pins,

12 Dedicated Input pins, four Dedicated Clock Input pins,

two dedicated Global OE input pins, and a Global Routing

Pool (GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 1048E fea-

tures 5V in-system programmability and in-system

diagnostic capabilities. The ispLSI 1048E offers non-

volatile reprogrammability of the logic, as well as the

interconnect to provide truly reconfigurable systems. A

functional superset of the ispLSI 1048 architecture, the

ispLSI 1048E device adds two new global output enable

pins and two additional dedicated inputs.

The basic unit of logic on the ispLSI 1048E device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1…F7 (see Figure 1). There are a total of 48 GLBs in the

ispLSI 1048E device. Each GLB has 18 inputs, a pro-

grammable AND/OR/Exclusive OR array, and four outputs

which can be configured to be either combinatorial or

registered. Inputs to the GLB come from the GRP and

dedicated inputs. All of the GLB outputs are brought back

into the GRP so that they can be connected to the inputs

of any other GLB on the device.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com

July 1998

1048E_08

Specifications ispLSI 1048E

Functional Block Diagram

Figure 1. ispLSI 1048E Functional Block Diagram

RESET

GOE 0

GOE 1

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

SDI/IN 0

MODE/IN 1

ispEN/NC

I/O I/O I/O I/O I/O I/O I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O IN IN

95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 11 10

I/O I/O I/O I/O I/O I/O I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O IN IN

79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 9 8

Generic

Logic Blocks

(GLBs)

Input Bus

Output Routing Pool (ORP)

F7 F6 F5 F4 F3 F2 F1 F0

Input Bus

Output Routing Pool (ORP)

E7 E6 E5 E4 E3 E2 E1 E0

Megablock

Global

Routing

Pool

(GRP)

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool (ORP)

Input Bus

C0 C1 C2 C3 C4 C5 C6 C7

Output Routing Pool (ORP)

Input Bus

Clock

Distribution

Network

CLK 0

CLK 1

CLK 2

IOCLK 0

IOCLK 1

IN 7

IN 6

I/O 63

I/O 62

I/O 61

I/O 60

I/O 59

I/O 58

I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

I/O 49

I/O 48

IN 2 SDO/ I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

IN 3 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

IN SCLK/ I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

4 IN 5 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Y Y Y Y 0139F(2)-48B-isp

0123

The device also has 96 I/O cells, each of which is directly

connected to an I/O pin. Each I/O cell can be individually

programmed to be a combinatorial input, registered in-

put, latched input, output or bi-directional

I/O pin with 3-state control. The signal levels are TTL

compatible voltages and the output drivers can source 4

mA or sink 8 mA. Each output can be programmed

independently for fast or slow output slew rate to mini-

mize overall output switching noise.

Eight GLBs, 16 I/O cells, two dedicated inputs and one

ORP are connected together to make a Megablock (see

figure 1). The outputs of the eight GLBs are connected to

a set of 16 universal I/O cells by the ORP. Each ispLSI

1048E device contains six Megablocks.

The GRP has, as its inputs, the outputs from all of the

GLBs and all of the inputs from the bi-directional I/O cells.

All of these signals are made available to the inputs of the

GLBs. Delays through the GRP have been equalized to

minimize timing skew.

Clocks in the ispLSI 1048E device are selected using the

Clock Distribution Network. Four dedicated clock pins

(Y0, Y1, Y2 and Y3) are brought into the distribution

network, and five clock outputs (CLK 0, CLK 1, CLK 2,

IOCLK 0 and IOCLK 1) are provided to route clocks to the

GLBs and I/O cells. The Clock Distribution Network can

also be driven from a special clock GLB (D0). The logic

of this GLB allows the user to create an internal clock

from a combination of internal signals within the device.

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ISPL1048E-100LQI 반도체 회로 부품 판매점

High-Density Programmable Logic

국내 전력반도체 판매점

일반적인 전자부품 판매점

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