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ATMEL Corporation |
Features
• Third Generation Programmable Logic Structure
– Easily Achieves Gate Utilization Factors of 80 Percent
• Increased Logic Flexibility
– 86 Inputs and 72 Sum Terms
• Flexible Output Macrocell
– 48 Flip-Flops - 2 per Macrocell
– 3 Sum Terms - Can Be OR'ed and Shared
• High-Speed
• Low-Power — Less than 0.5 mA Typical (ATV2500L)
• Multiple Feedback Paths Provide for Buried State Machines
and I/O Bus Compatibility
• Asynchronous Clocks and Resets
– Multiple Synchronous Presets - One per Four or Eight Flip-Flops
• Proven and Reliable High Speed CMOS EPROM Process
– 2000V ESD Protection
– 200 mA Latchup Immunity
• Reprogrammable - Tested 100% for Programmability
• 40-pin Dual-In-line and 44-Lead Surface Mount Packages
Block Diagram
High-Density
UV-Erasable
Programmable
Logic Device
ATV2500H
ATV2500L
Description
The ATV2500H/L is the most powerful programmable logic device available in a 40-
pin package. Increased product terms, sum terms, and flip-flops translate into many
more usable gates. High gate utilization is easily obtainable.
The ATV2500H/L is organized around a global bus. All pin and feedback terms are
always available to every logic cell. Each of the 38 logic pins and their complements
are array inputs, as well as the true and false outputs of each of the 48 flip-flops.
(continued)
Pin Configurations
DIP
PLCC/LCC
Pin Name
IN
I/O
I/O, 0,2,4..
I/O, 1,3,5..
*
VCC
Function
Logic Inputs
Bidirectional Buffers
“Even” I/O Buffers
“Odd” I/O Buffers
No Internal Connection
+5V Supply
IN
IN
IN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
IN
IN
IN
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 IN
39 IN
38 IN
37 IN
36 I/O6
35 I/O7
34 I/O8
33 I/O9
32 I/O10
31 I/O11
30 GND
29 I/O23
28 I/O22
27 I/O21
26 I/O20
25 I/O19
24 I/O18
23 IN
22 IN
21 IN
I/O2
I/O3
I/O4
I/O5
VCC
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
7
8
9
10
11
12
13
14
15
16
17
* = No Connect
39 I/O7
38 I/O8
37 I/O9
36 I/O10
35 I/O11
34 GND
33 GND
32 I/O23
31 I/O22
30 I/O21
29 I/O20
Rev. 0025E–05/98
1
There are 416 product terms available. Four product terms
are input to each sum term. The three sum terms per logic
cell can be combined to provide up to twelve product terms,
combinatorial and registered. Independent of output config-
uration, the two flip-flops are always usable, and always
have at least four product term inputs.
Product terms are available providing asynchronous
resets, flip-flop clocks, and output enables. One reset and
one clock term are provided per flip-flop, with one enable
term per output. Eight product terms provide local synchro-
nous presets, divided up into banks of four and eight flip-
flops. Register preload and buried register observability
simplify testing. The device has an internal power up clear
function.
Functional Logic Diagram ATV2500H/L
2 ATV2500H/L
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