CY7C4211V 반도체 회로 부품 판매점
Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
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 Cypress Semiconductor |
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Features
Functional Description
• High-speed, low-power, first-in, first-out (FIFO)
memories
• 64 x 9 (CY7C4421V)
• 256 x 9 (CY7C4201V)
• 512 x 9 (CY7C4211V)
• 1K x 9 (CY7C4221V)
• 2K x 9 (CY7C4231V)
• 4K x 9 (CY7C4241V)
• 8K x 9 (CY7C4251V)
• High-speed 66-MHz operation (15-ns read/write cycle
time)
• Low power (ICC = 20 mA)
• 3.3V operation for low power consumption and easy
integration into low-voltage systems
• 5V-tolerant inputs VIH max= 5V
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, and Programmable Almost Empty and
Almost Full status flags
• TTL compatible
• Output Enable (OE) pin
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Width expansion capability
• Space saving 32-pin 7 mm × 7 mm TQFP
• 32-pin PLCC
The CY7C42X1V are high-speed, low-power, FIFO memories
with clocked read and write interfaces. All are nine bits wide.
Programmable features include Almost Full/Almost Empty
flags. These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition, multi-
processor interfaces, and communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a Free-Running Clock (WCLK) and two Write
Enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a Free-Running Read Clock (RCLK) and
two Read Enable Pins (REN1, REN2). In addition, the
CY7C42X1V has an Output Enable Pin (OE). The Read
(RCLK) and Write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock
frequencies up to 66 MHz are achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data.
Logic Block Diagram
WCLK WEN1 WEN2/LD
WRITE
CONTROL
WRITE
POINTER
D0 − 8
INPUT
REGISTER
Dual Port
RAM Array
64 x 9
8Kx 9
Pin Configuration
PLCC
Top View
FLAG
PROGRAM
REGISTER
FLAG
LOGIC
READ
POINTER
EF
PAE
PAF
FF
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
OE
4 3 2 1 32 3130
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 22
13 21
141516 171819 20
RS
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
TQFP
Top View
RS
RESET
LOGIC
THREE-STATE
OUTPUTREGISTER
Q0 − 8
OE
READ
CONTROL
RCLK REN1 REN2
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-06010 Rev. *A
Revised August 22, 2003
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Selection Guide
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
Active Power Supply Current
Commercial
CY7C42X1V-15
66.7
11
15
4
1
10
20
CY7C42X1V-25
40
15
25
6
1
15
20
CY7C42X1V-35
28.6
20
35
7
2
20
20
Unit
MHz
ns
ns
ns
ns
ns
mA
Density
CY7C4421V CY7C4201V CY7C4211V CY7C4221V CY7C4231V CY7C4241V CY7C4251V
64 x 9
256 x 9
512 x 9
1K x 9
2K x 9
4K x 9
8K x 9
Pin Definitions
Signal Name Description
D0−8
Q0−8
WEN1
Data Inputs
Data Outputs
Write Enable 1
WEN2/LD
Write Enable 2
Dual Mode Pin Load
REN1, REN2
WCLK
Read Enable
Inputs
Write Clock
RCLK
Read Clock
EF Empty Flag
FF Full Flag
PAE Programmable
Almost Empty
PAF Programmable
Almost Full
RS Reset
OE Output Enable
I/O Description
I Data Inputs for 9-bit bus.
O Data Outputs for 9-bit bus.
I The only write enable when device is configured to have programmable flags.
Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is
HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
I If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this
I
pin operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW
to write or read the programmable flag offsets.
I Enables the device for Read operation.
I The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
I The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the
FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag
offset register.
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO.
O When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO.
I Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If
OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Functional Description (continued)
The CY7C42X1V provides four status pins: Empty, Full, Almost
Empty, Almost Full. The Almost Empty/Almost Full flags are program-
mable to single word granularity. The programmable flags default to
Empty-7 and Full-7.
The flags are synchronous, i.e., they change state relative to
either the Read Clock (RCLK) or the Write Clock (WCLK).
When entering or exiting the Empty and Almost Empty states,
the flags are updated exclusively by the RCLK. The flags
denoting Almost Full and Full states are updated exclusively
by WCLK. The synchronous flag architecture guarantees that
the flags maintain their status for at least one cycle
All configurations are fabricated using an advanced 0.65m
P-Well CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Document #: 38-06010 Rev. *A
Page 2 of 17
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( cypress )
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