CY37512P208-83NC 반도체 회로 부품 판매점
5V/ 3.3V/ ISR High-Performance CPLDs
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 Cypress Semiconductor |
Ultra37000 CPLD Family
5V, 3.3V, ISR™ High-Performance CPLDs
Features
General Description
• In-System Reprogrammable™ (ISR™) CMOS CPLDs
— JTAG interface for reconfigurability
— Design changes do not cause pinout changes
— Design changes do not cause timing changes
• High density
— 32 to 512 macrocells
— 32 to 264 I/O pins
— Five dedicated inputs including four clock pins
• Simple timing model
— No fanout delays
— No expander delays
— No dedicated vs. I/O pin delays
— No additional delay through PIM
— No penalty for using full 16 product terms
— No delay for steering or sharing product terms
• 3.3V and 5V versions
• PCI-compatible[1]
• Programmable bus-hold capabilities on all I/Os
• Intelligent product term allocator provides:
— 0 to 16 product terms to any macrocell
— Product term steering on an individual basis
The Ultra37000™ family of CMOS CPLDs provides a range of
high-density programmable logic solutions with unparalleled
system performance. The Ultra37000 family is designed to
bring the flexibility, ease of use, and performance of the 22V10
to high-density CPLDs. The architecture is based on a number
of logic blocks that are connected by a Programmable Inter-
connect Matrix (PIM). Each logic block features its own
product term array, product term allocator, and 16 macrocells.
The PIM distributes signals from the logic block outputs and all
input pins to the logic block inputs.
All of the Ultra37000 devices are electrically erasable and In-
System Reprogrammable (ISR), which simplifies both design
and manufacturing flows, thereby reducing costs. The ISR
feature provides the ability to reconfigure the devices without
having design changes cause pinout or timing changes. The
Cypress ISR function is implemented through a JTAG-
compliant serial interface. Data is shifted in and out through
the TDI and TDO pins, respectively. Because of the superior
routability and simple timing model of the Ultra37000 devices,
ISR allows users to change existing logic designs while simul-
taneously fixing pinout assignments and maintaining system
performance.
The entire family features JTAG for ISR and boundary scan,
and is compatible with the PCI Local Bus specification,
meeting the electrical and timing requirements. The
Ultra37000 family features user programmable bus-hold
capabilities on all I/Os.
— Product term sharing among local macrocells
• Flexible clocking
— Four synchronous clocks per device
— Product term clocking
— Clock polarity control per logic block
• Consistent package/pinout offering across all densities
— Simplifies design migration
Ultra37000 5.0V Devices
The Ultra37000 devices operate with a 5V supply and can
support 5V or 3.3V I/O levels. VCCO connections provide the
capability of interfacing to either a 5V or 3.3V bus. By
connecting the VCCO pins to 5V the user insures 5V TTL levels
on the outputs. If VCCO is connected to 3.3V the output levels
meet 3.3V JEDEC standard CMOS levels and are 5V tolerant.
These devices require 5V ISR programming.
— Same pinout for 3.3V and 5.0V devices
Ultra37000V 3.3V Devices
• Packages
— 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP,
Devices operating with a 3.3V supply require 3.3V on all VCCO
pins, reducing the device’s power consumption. These
BGA, and Fine-Pitch BGA packages
devices support 3.3V JEDEC standard CMOS output levels,
and are 5V-tolerant. These devices allow 3.3V ISR
programming.
Note:
1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to VCC, PCI VIH = 2V.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03007 Rev. *C
Revised July 7, 2003
Ultra37000 CPLD Family
Selection Guide
5.0V Selection Guide
General Information
Device
CY37032
CY37064
CY37128
CY37192
CY37256
CY37384
CY37512
Macrocells
32
64
128
192
256
384
512
Dedicated
Inputs
5
5
5
5
5
5
5
I/O Pins
32
32/64
64/128
120
128/160/192
160/192
160/192/264
Speed (tPD)
6
6
6.5
7.5
7.5
10
10
Speed (fMAX)
200
200
167
154
154
118
118
Speed Bins
Device
200
167
154
143
125
100
CY37032
X
X
X
CY37064
X
X
X
CY37128
X
XX
CY37192
XX
CY37256
XX
CY37384
X
CY37512
XX
83
X
X
X
X
66
Device-Package Offering and I/O Count
Device
CY37032
CY37064
CY37128
CY37192
CY37256
CY37384
CY37512
44-
Lead
TQFP
37
37
44-
Lead
PLCC
37
37
44-
Lead
CLCC
37
84-
Lead
PLCC
69
69
84-
Lead
CLCC
69
100-
Lead
TQFP
69
69
160-
Lead
TQFP
133
125
133
160-
Lead
CQFP
133
208-
Lead
PQFP
165
165
165
208-
Lead
CQFP
165
256-
Lead
BGA
197
197
197
352-
Lead
BGA
269
3.3V Selection Guide
General Information
Device
CY37032V
CY37064V
CY37128V
CY37192V
CY37256V
CY37384V
CY37512V
Macrocells
32
64
128
192
256
384
512
Dedicated
Inputs
5
5
5
5
5
5
5
I/O Pins
32
32/64
64/80/128
120
128/160/192
160/192
160/192/264
Speed (tPD)
8.5
8.5
10
12
12
15
15
Speed (fMAX)
143
143
125
100
100
83
83
Document #: 38-03007 Rev. *C
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CY37512P208-83NC
5V/ 3.3V/ ISR High-Performance CPLDs - Cypress Semiconductor
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5V/ 3.3V/ ISR High-Performance CPLDs - Cypress Semiconductor