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ADSP-BF532 반도체 회로 부품 판매점

Blackfin Embedded Processor



Analog Devices 로고
Analog Devices
ADSP-BF532 데이터시트, 핀배열, 회로
Blackfin
Embedded Processor
ADSP-BF531/ADSP-BF532/ADSP-BF533
FEATURES
Up to 600 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of pro-
gramming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Wide range of operating voltages (see Operating Conditions
on Page 20)
Qualified for Automotive Applications (see Automotive Prod-
ucts on Page 62)
Programmable on-chip voltage regulator
160-ball CSP_BGA, 169-ball PBGA, and 176-lead LQFP
packages
MEMORY
Up to 148K bytes of on-chip memory (see Table 1 on Page 3)
Memory management unit providing memory protection
External memory controller with glueless support for
SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI and
external memory
PERIPHERALS
Parallel peripheral interface PPI, supporting
ITU-R 656 video data formats
2 dual-channel, full duplex synchronous serial ports, sup-
porting eight stereo I2S channels
2 memory-to-memory DMAs
8 peripheral DMAs
SPI-compatible port
Three 32-bit timer/counters with PWM support
Real-time clock and watchdog timer
32-bit core timer
Up to 16 general-purpose I/O pins (GPIO)
UART with support for IrDA
Event handler
Debug/JTAG interface
On-chip PLL capable of frequency multiplication
VOLTAGE REGULATOR
JTAG TEST AND EMULATION
B
INTERRUPT
CONTROLLER
L1
INSTRUCTION
MEMORY
L1
DATA
MEMORY
DMA
CONTROLLER
DMA CORE BUS
EXTERNAL ACCESS BUS
EXTERNAL PORT
FLASH, SDRAM CONTROL
DMA
EXTERNAL
BUS
16
BOOT ROM
WATCHDOG
TIMER
RTC
PPI
TIMER0-2
SPI
UART
SPORT0-1
GPIO
PORT
F
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. I
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com


ADSP-BF532 데이터시트, 핀배열, 회로
ADSP-BF531/ADSP-BF532/ADSP-BF533
TABLE OF CONTENTS
Features ................................................................. 1
Memory ................................................................ 1
Peripherals ............................................................. 1
General Description ................................................. 3
Portable Low Power Architecture ............................. 3
System Integration ................................................ 3
Processor Peripherals ............................................. 3
Blackfin Processor Core .......................................... 4
Memory Architecture ............................................ 4
DMA Controllers .................................................. 8
Real-Time Clock ................................................... 8
Watchdog Timer .................................................. 9
Timers ............................................................... 9
Serial Ports (SPORTs) ............................................ 9
Serial Peripheral Interface (SPI) Port ....................... 10
UART Port ........................................................ 10
General-Purpose I/O Port F ................................... 10
Parallel Peripheral Interface ................................... 11
Dynamic Power Management ................................ 11
Voltage Regulation .............................................. 13
Clock Signals ..................................................... 13
Booting Modes ................................................... 14
Instruction Set Description ................................... 15
Development Tools .............................................. 15
Additional Information ........................................ 16
Related Signal Chains ........................................... 16
Pin Descriptions .................................................... 17
Specifications ........................................................ 20
Operating Conditions ........................................... 20
Electrical Characteristics ....................................... 22
Absolute Maximum Ratings ................................... 25
ESD Sensitivity ................................................... 25
Package Information ............................................ 26
Timing Specifications ........................................... 27
Output Drive Currents ......................................... 43
Test Conditions .................................................. 45
Thermal Characteristics ........................................ 49
160-Ball CSP_BGA Ball Assignment ........................... 50
169-Ball PBGA Ball Assignment ................................. 53
176-Lead LQFP Pinout ............................................ 56
Outline Dimensions ................................................ 58
Surface-Mount Design .......................................... 61
Automotive Products .............................................. 62
Ordering Guide ..................................................... 63
REVISION HISTORY
8/13— Rev. H to Rev. I
Updated Development Tools .................................... 15
Corrected Conditions value of the VIL specification in
Operating Conditions ............................................. 20
Added notes to Table 30 in
Serial Ports—Enable and Three-State .......................... 36
Added Timer Clock Timing ...................................... 41
Revised Timer Cycle Timing ..................................... 41
Updated Ordering Guide ......................................... 63
Rev. I | Page 2 of 64 | August 2013




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