AT49BV1614-12CC 반도체 회로 부품 판매점
16-megabit (1M x 16/2M x 8) 3-volt Only Flash Memory
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 ATMEL Corporation |
Features
• 2.7V to 3.3V Read/Write
• Access Time - 90 ns
• Sector Erase Architecture
– Thirty 32K Word (64K Byte) Sectors with Individual Write Lockout
– Eight 4K Word (8K Byte) Sectors with Individual Write Lockout
– Two 16K Word (32K Byte) Sectors with Individual Write Lockout
• Fast Word Program Time - 20 µs
• Fast Sector Erase Time - 200 ms
• Dual Plane Organization, Permitting Concurrent Read while Program/Erase
Memory Plane A: Eight 4K Word, Two 16K Word and Six 32K Word Sectors
Memory Plane B: Twenty-four 32K Word Sectors
• Erase Suspend Capability
– Supports Reading/Programming Data from Any Sector by Suspending Erase of
Any Different Sector
• Low-power Operation
– 25 mA Active
– 10 µA Standby
• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
• Optional VPP Pin for Fast Programming
• RESET Input for Device Initialization
• Sector Program Unlock Command
• TSOP, CBGA, and µBGA Package Options
• Top or Bottom Boot Block Configuration Available
Description
The AT49BV16X4(T) is 2.7- to 3.3-volt 16-megabit Flash memory organized as
1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data
appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided
into 40 sectors for erase operations. The device is offered in 48-pin TSOP and 48-ball
µBGA packages. The device has CE, and OE control signals to avoid any bus
(continued)
Pin Configurations
Pin Name
A0 - A19
CE
OE
WE
RESET
RDY/BUSY
VPP
I/O0 - I/O14
I/O15 (A-1)
BYTE
NC
VCCQ
DC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
READY/BUSY Output
Optional Power Supply for Faster
Program/Erase Operations
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
Output Power Supply
Don’t Connect
16-megabit
(1M x 16/2M x 8)
3-volt Only
Flash Memory
AT49BV1604
AT49BV1604T
AT49BV1614
AT49BV1614T
Rev. 0925H–08/99
1
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
VPP
NC
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TSOP Top View
Type 1
48 A16
47 VCCQ
46 GND
45 I/O15
44 I/O7
43 I/O14
42 I/O6
41 I/O13
40 I/O5
39 I/O12
38 I/O4
37 VCC
36 I/O11
35 I/O3
34 I/O10
33 I/O2
32 I/O9
31 I/O1
30 I/O8
29 I/O0
28 OE
27 GND
26 CE
25 A0
TSOP Top View
Type 1
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
RESET
VPP
NC
RDY/BUSY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 A16
47 BYTE
46 GND
45 I/O15/A-1
44 I/O7
43 I/O14
42 I/O6
41 I/O13
40 I/O5
39 I/O12
38 I/O4
37 VCC
36 I/O11
35 I/O3
34 I/O10
33 I/O2
32 I/O9
31 I/O1
30 I/O8
29 I/O0
28 OE
27 GND
26 CE
25 A0
AT49BV1604(T)
AT49BV1614(T)
µBGA Top View (Ball Down)
1 2 3 4 5 6 78
A
A13 A11 A8 VPP
B
A19 A7 A4
A14 A10 WE RST A18 A17 A5 A2
C
A15 A12 A9
D
A6 A3 A1
A16 I/O14 I/O5 I/O11 I/O2 I/O8 CE A0
E
VCCQ I/O15 I/O6 I/O12 I/O3 I/O9 I/O0 GND
F
GND I/O7 I/O13 I/O4 VCC I/O10 I/O1 OE
CBGA Top View
12345
6
A
A3 A7 RDY/BUSY WE A9 A13
B
A4 A17 NC RESET A8 A12
C
A2 A6 A18 VPP A10 A14
D
A1 A5 NC A19 A11 A15
E
A0 I/O0 I/O2 I/O5 I/O7 A16
F
CE I/O8 I/O10 I/O12 I/O14 BYTE
G
OE I/O9 I/O11 VCC I/O13 I/O15
/A-1
H
VSS I/O1 I/O3 I/O4 I/O6 VSS
contention. This device can be read or reprogrammed
using a single 2.7V power supply, making it ideally suited
for in-system programming.
The device powers on in the read mode. Command
sequences are used to place the device in other operation
modes such as program and erase. The device has the
capability to protect the data in any sector. Once the data
protection for a given sector is enabled, the data in that
sector cannot be changed using input levels between
ground and VCC.
The device is segmented into two memory planes. Reads
from memory plane B may be performed even while
program or erase functions are being executed in memory
plane A and vice versa. This operation allows improved
system performance by not requiring the system to wait for
a program or erase operation to complete before a read is
performed. To further increase the flexibility of the device, it
contains an Erase Suspend feature. This feature will put
the Erase on hold for any amount of time and let the user
read data from or program data to any of the remaining
sectors within the same memory plane. There is no reason
to suspend the erase operation if the data to be read is in
the other memory plane. The end of a program or an Erase
cycle is detected by the Ready/Busy pin, Data polling, or by
the toggle bit.
2 AT49BV1604(T)/1614(T)
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( atmel )
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관련 데이터시트
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