CAT64LC40 반도체 회로 부품 판매점
1K/2K/4K-Bit SPI Serial E2PROM
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 Catalyst Semiconductor |
CAT64LC10/20/40
1K/2K/4K-Bit SPI Serial EEPROM
FEATURES
s SPI bus compatible
s Low power CMOS technology
s 2.5V to 6.0V operation
s Self-timed write cycle with auto-clear
s Hardware reset pin
s Hardware and software write protection
ALOGEN FR
LEA D F REETM
s Commercial, industrial and automotive
temperature ranges
s Power-up inadvertant write protection
s RDY/BSY pin for end-of-write indication
s 1,000,000 program/erase cycles
s 100 year data retention
DESCRIPTION
The CAT64LC10/20/40 is a 1K/2K/4K-bit Serial EEPROM
which is configured as 64/128/256 registers by 16 bits.
Each register can be written (or read) serially by using
the DI (or DO) pin. The CAT64LC10/20/40 is
manufactured using Catalyst’s advanced CMOS
EEPROM floating gate technology. It is designed to
endure 1,000,000 program/erase cycles and has a data
retention of 100 years. The device is available in 8-pin
DIP, SOIC and TSSOP packages.
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J, W)
CS 1
SK 2
DI 3
DO 4
8 VCC
RDY/BUSY
7 RDY/BUSY
VCC
6 RESET
CS
5 GND
SK
1
2
3
4
8 RESET
7 GND
6 DO
5 DI
TSSOP Package (U, Y)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 RDY/BUSY
6 RESET
5 GND
SOIC Package (S, V)
TSSOP Package (UR, YR)
CS 1
SK 2
DI 3
DO 4
8 VCC
RDY/BUSY 1
7 RDY/BUSY
6 RESET
VCC 2
CS 3
5 GND
SK 4
8 RESET
7 GND
6 DO
5 DI
PIN FUNCTIONS
Pin Name
Function
CS Chip Select
SK Clock Input
DI Serial Data Input
DO Serial Data Output
VCC +2.5V to +6.0V Power Supply
GND
Ground
RESET
Reset
RDY/BUSY
Ready/BUSY Status
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
BLOCK DIAGRAM
VCC
GND
MEMORY ARRAY
64/128/256 x 16
ADDRESS
DECODER
DI
RESET
CS
SK
DATA
REGISTER
MODE DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
DO RDY/BUSY
64LC10/20/40 F02
Doc. No. 1021, Rev. B
1
CAT64LC10/20/40
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to Ground(1) ............ –2.0V to +VCC +2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
RELIABILITY CHARACTERISTICS
Symbol
NEND(3)
TDR(3)
VZAP(3)
ILTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
1,000,000
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
CAPACITANCE (TA = 25°C, f= 1.0 MHz, VCC =6.0V)
Symbol
Test
CI/O(3)
Input/Output Capacitance (DO, RDY/BSY)
CIN(3)
Input Capacitance (CS, SK, DI, RESET)
Max.
8
6
Units
pF
pF
Conditions
VI/O = 0V
VIN = 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
Doc. No. 1021, Rev. B
2
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CAT64LC40 data
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[ CAT64LC40.PDF ]
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