CAT5401 반도체 회로 부품 판매점
Quad Digitally Programmable Potentiometers (DPP) with 64 Taps and SPI Interface
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 Catalyst Semiconductor |
CAT5401
Quad Digitally Programmable Potentiometers (DPP™)
with 64 Taps and SPI Interface
FEATURES
ALOGEN FR
LEA D F REETM
s Four linear-taper digitally programmable
potentiometers
s 64 resistor taps per potentiometer
s End to end resistance 2.5kΩ, 10kΩ, 50kΩ or 100kΩ
s Potentiometer control and memory access via
SPI interface: Mode (0, 0) and (1, 1)
s Low wiper resistance, typically 80Ω
s Nonvolatile memory storage for up to four wiper
settings for each potentiometer
s Automatic recall of saved wiper settings at
power up
s 2.5 to 6.0 volt operation
s Standby current less than 1µA
s 1,000,000 nonvolatile WRITE cycles
s 100 year nonvolatile memory data retention
s 24-lead SOIC, 24-lead TSSOP and BGA
s Industrial temperature range
DESCRIPTION
The CAT5401 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists of
a series of 63 resistive elements connected between two
externally accessible end points. The tap points between
each resistive element are connected to the wiper outputs
with CMOS switches. A separate 6-bit control register
(WCR) independently controls the wiper tap switches for
each DPP. Associated with each wiper control register
are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the
wiper control register or any of the non-volatile data
registers is via a SPI serial bus. On power-up, the
contents of the first data register (DR0) for each of the
four potentiometers is automatically loaded into its
respective wiper control register.
The CAT5401 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
SOIC Package (J, W)
TSSOP Package (U, Y)
VCC
RL0
RH0
RW0
CS
WP
SI
A1
RL1
RH1
RW1
GND
1 24
2 23
3 22
4 21
5 20
6 CAT 19
7 5401 18
8 17
9 16
10 15
11 14
12 13
NC SI
RL3
RH3
RW3
A0
SO
A1
RL1
RH1
RW1
GND
HOLD NC
SCK
RL2
RW2
RH2
RH2 RL2
RW2 SCK
NC HOLD
1 24
2 23
3 22
4 21
5 20
6 CAT 19
7 5401 18
8 17
9 16
10 15
11 14
12 13
WP
CS
RW0
RH0
RL0
VCC
NC
RL3
RH3
RW3
A0
SO
FUNCTIONAL DIAGRAM
RH0 RH1 RH2 RH3
CS
SCK
SI
SO
SPI BUS
INTERFACE
WIPER
CONTROL
REGISTERS
WP CONTROL NONVOLATILE
A0 LOGIC
DATA
A1 REGISTERS
RL0 RL1 RL2 RL3
A
B
BGA C
D
E
F
1
RW0
RL0
VCC
NC
RL3
RW3
234
CS A1 RL1
WP
RH0
SI
RH1
RW1
VSS
RH3
SO
A0
RH2
HOLD
SCK
NC
RW2
RL2
Top View - Bump Side Down
R W0
R W1
R W2
R W3
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Document No. 2010, Rev. F
CAT5401
PIN DESCRIPTION
PIN DESCRIPTIONS
Pin Pin Pin
(SOIC) (TSSOP) (BGA) Name
1 19 C1 VCC
2 20 B1 RL0
3 21 C2 RH0
4 22 A1 RW0
5 23 A2 CS
6 24 B2 WP
7 1 B3 SI
8 2 A3 A1
9 3 A4 RL1
10 4 C3 RH1
Function
Supply Voltage
Low Reference Terminal
for Potentiometer 0
High Reference Terminal
for Potentiometer 0
Wiper Terminal for Potentiometer 0
Chip Select
Write Protection
Serial Input
Device Address
Low Reference Terminal
for Potentiometer 1
High Reference Terminal
for Potentiometer 1
SI: Serial Input
SI is the serial data input pin. This pin is used to input
all opcodes, byte addresses and data to be written to
the CAT5401. Input data is latched on the rising edge
of the serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the CAT5401. During a read
cycle, data is shifted out on the falling edge of the
serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to
synchronize the communication between the
microcontroller and the CAT5401. Opcodes, byte
addresses or data present on the SI pin are latched
on the rising edge of the SCK. Data on the SO pin is
updated on the falling edge of the SCK.
11 5 B4 RW1 Wiper Terminal for Potentiometer 1 A0, A1: Device Address Inputs
12 6 C4 GND Ground
These inputs set the device address when address-
ing multiple devices. A total of four devices can be
13 7 D4 NC No Connect
addressed on a single bus. A match in the slave
14 8 E4 RW2 Wiper Terminal for
Potentiometer 2
address must be made with the address input in
order to initiate communication with the CAT5401.
15 9 D3 RH2 High Reference Terminal
for Potentiometer 2
16 10 F4 RL2 Low Reference Terminal
RH, RL: Resistor End Points
The four sets of RH and RL pins are equivalent to the
terminal connections on a mechanical potentiometer.
for Potentiometer 2
17 11 F3 SCK Bus Serial Clock
18 12 E3 HOLD Hold
RW: Wiper
The four RW pins are equivalent to the wiper terminal
of a mechanical potentiometer.
19 13 E2 SO Serial Data Output
20 14 F2 A0 Device Address, LSB
CS: Chip Select
CS is the Chip select pin. CS low enables the
CAT5401 and CS high disables the CAT5401. CS high
21 15 F1 RW3 Wiper Terminal for Potentiometer 3 takes the SO output pin to high impedance and forces
22 16 D2 RH3 High Reference Terminal
for Potentiometer 3
23 17 E1 RL3 Low Reference Terminal
for Potentiometer 3
24 18 D1 NC No Connect
the devices into a Standby mode (unless an internal
write operation is underway). The CAT5401 draws
ZERO current in the Standby mode. A high to low
transition on CS is required prior to any sequence
being initiated. A low to high transition on CS after a
valid write sequence is what initiates an internal write
cycle.
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low, all
non-volatile write operations to the Data registers are inhibited (change of wiper control register is allowed). WP going low while
CS is still low will interrupt a write to the registers. If the internal write cycle has already been initiated, WP going low will have no
effect on any write operation.
HOLD: Hold
The HOLD pin is used to pause transmission to the CAT5401 while in the middle of a serial sequence without having to re-
transmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high imped-
ance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is
brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high
directly to VCC or tied to VCC through a resistor.
Document No. 2010, Rev. F
2
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CAT5401 data
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