TPS65030 반도체 회로 부품 판매점
TPS65030 Power-Management IC for USB-OTG (Rev. C)
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 Texas |
TPS65030
www.ti.com
SLVS620B – FEBRUARY 2006 – REVISED JULY 2007
POWER MANAGEMENT IC for USB-OTG
FEATURES
• 4 Regulated Output Voltages with 3%
Tolerance
– Fractional Charge Pump for 5 V/100 mA
– Fractional Charge Pump for 1.5 V/200 mA
– Doubling Charge Pump With LDO Mode for
3.3 V/22 mA
– LDO for 1.8 V/60 mA
• Switching Frequency 1 MHz
• 3 V to 5 V Operating Input Voltage Range at
VCC Pin
• Sleep Mode Sets Vout2 and Vout3 Into LDO
Mode
• Sleep Mode Reduces Quiescent Current of
Vout2, Vout3, and Vout4 to 8 μA Each
• internal Bus Switch
• Vbus Comparator
• Internal Soft Start Limits Inrush Current
• Low Input Current Ripple and Low EMI
• Overcurrent and Overtemperature Protected
• Undervoltage Lockout With Hysteresis
• Ultra-Small 2,5 mm x 2,7 mm Chip Scale
Package Applications
APPLICATIONS
• Power Supply for USB OTG for:
– Cellular Phones
– Smart Phones
– PDAs
– Handheld PCs
– Digital Cameras
– Camcorders
DESCRIPTION
The TPS65030 contains three charge pumps and
one LDO to generate all supply voltages necessary
for an USB On-The-Go (OTG) implementation using
TUSB6010. The charge pumps are optimized for a
single Li-Ion cell input or for 5 V from the USB bus.
The input voltage range is 3 V to 5 V for the battery
voltage. High efficiency is achieved by using
fractional conversion techniques for the charge
pumps in combination with a power saving sleep
mode. The current controlled charge pumps in
addition ensure low input current ripple and low EMI.
Small size external ceramic capacitors are required
to build a complete power supply solution. To reduce
board space to a minimum, the device switches at
1-MHz operating frequency, and is available in a
small 25-ball chip scale package (YZK).
3 V . . .4.2 V (5 V)
10 mF
TPS65030
VIN Vbus
VIN
EN1 (5 V)
EN2 (3.3 V
and 1.5 V)
EN3 (1.8 V)
SLEEP
Charge CF1A+
Pump
CF1A−
CF1B+
CF1B−
Vout2
PGood
SW_EN1
Charge CF2+
Pump
CF2−
SW_EN2
Test SRP
PGND
PGND
GND
Vout3
Charge CF3+
Pump
CF3−
Vout4
LDO
Co1
4.7 mF
1 mF
1 mF
Co2
1 mF
100 nF
Co3
10 mF
1 mF
Co4
1 mF
5 V/100 mA
3.3 V/22 mA
1.5 V/200 mA
1.8 V/60 mA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
TPS65030
SLVS620B – FEBRUARY 2006 – REVISED JULY 2007
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGED DEVICES(1)
PACKAGE
TPS65030YZK
Chip scale
MARKING
PJMI
(1) The YZK package is available in tape and reel. Add R suffix (TPS65030YZKR) to order quantities of
3000 parts per reel. Add T suffix (TPS65030YZKT) to order quantities of 250 parts per reel.
PACKAGE DIMENSIONS
PACKAGED DEVICES (1)
D MAXIMUM
TPS65030YZK
2,708 mm
E MAXIMUM
2,51 mm
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VS Supply voltage at VIN, Vbus
Voltage at EN1, EN2, EN3, SLEEP, SW_EN1, SW_EN2, PG, Test SRP
Output current at Vbus
Output current at Vout2
IO Output current at Vout3
Output current at Vout4
TJ Maximum junction temperature,
TA Operating free-air temperature,
Tstg Storage temperature,
VALUE
–0.3 to 7
–0.3 V to VIN
200
40
300
100
150
–40 to 85
-65 to 150
UNIT
V
mA
mA
mA
mA
°C
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges; HBM according to EIA/JESD22-A114-B; MM
according EIA/JESD22-A115-A and CDM according EIA/JESD22C101C, however, it is advised that precautions should be taken to
avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the
device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be
connected to an appropriated logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type
are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available
from Texas Instruments.
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