IS43DR32801B 반도체 회로 부품 판매점
8Mx32 256Mb DDR2 DRAM
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 ISSI |
IS43/46DR32801B
8Mx32
256Mb DDR2 DRAM
FEATURES
• Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Double data rate interface: two data transfers
per clock cycle
• Differential data strobe (DQS, DQS)
• 4-bit prefetch architecture
• On chip DLL to align DQ and DQS transitions
with CK
• 4 internal banks for concurrent operation
• Programmable CAS latency (CL) 3, 4, 5, and 6
supported
• Posted CAS and programmable additive latency
(AL) 0, 1, 2, 3, 4, and 5 supported
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength, full and
reduced strength options
• On-die termination (ODT)
OPTIONS
• Configuration:
8M x 32 (IS43/46DR32801B - 8K refresh)
• Package: x32: 126-ball WBGA
• Timing – Cycle time
2.5ns @CL=6, DDR2-800E
3.0ns @CL=5, DDR2-667D
3.75ns @CL=4, DDR2-533C
5.0ns @CL=3, DDR2-400B
• Temperature Range:
Commercial (0°C ≤ Tc ≤ 85°C; 0°C ≤ Ta ≤ 70°C)
Industrial (–40°C ≤ Tc ≤ 95°C; –40°C ≤ Ta ≤ 85°C)
Automotive, A1 (–40°C ≤ Tc ≤ 95°C; –40°C ≤ Ta ≤ 85°C)
Automotive, A2 (–40°C ≤ Tc ≤ 105°C; –40°C ≤ Ta ≤ 105°C)
Tc = Case Temp, Ta = Ambient Temp
ADVANCED INFORMATION
JUNE 2012
DESCRIPTION
ISSI's 256Mb DDR2 SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The
double-data rate architecture is essentially a 4n-prefetch
architecture, with an interface designed to transfer two
data words per clock cycle at the I/O balls.
The 256Mb DDR2 SDRAM is provided in a wide bus
x32 format, designed to offer a smaller footprint and
support compact designs.
ADDRESS TABLE
Parameter
Configuration
Refresh Count
Row Addressing
Column
Addressing
Bank Addressing
Precharge
Addressing
8M x 32
4M x 32 x 4 banks
8K/64ms
A0-A12
A0-A7
BA0, BA1
A10/AP
KEY TIMING PARAMETERS
Speed Grade -25E -3D -37C
tRCD
15 15 15
tRP 15 15 15
tRC 60 60 60
tRAS
45 45 45
tCK @CL=3
555
tCK @CL=4
3.75 3.75 3.75
tCK @CL=5
3 3 3.75
tCK @CL=6
2.5 3 3.75
-5B
15
15
55
40
5
5
5
5
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
06/07/2012
1
IS43/46DR32801B
General Description
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue
for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write command. The address bits registered coincident with the active
command are used to select the bank and row to be accessed (BA0-BA1 select the bank; A0-A12 select the row and
A0-A7 select the column). The address bits registered coincident with the Read or Write command are used to select
the starting column location for the burst access and to determine if the auto precharge command is to be issued.
Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information
covering device initialization, register definition, command descriptions and device operation.
Functional Block Diagram
CK
CK
CKE
ODT
CS
RAS
CAS
WE
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTERS
A0 – A12,
BA0 – BA1
ROW
ADDRESS
LATCH
COLUMN
ADDRESS LATCH
BURST COUNTER
COLUMN ADDRESS
BUFFER
REFRESH
CONTROLLER
SELF
REFRESH
CONTROLLER
REFRESH
COUNTER
ROW
ADDRESS
BUFFER
BANK CONTROL LOGIC
DQ0 – DQ31
DLL
MEMORY CELL
ARRAY
MEMORY CELL
ARRABYANK 0
BANK 0
SENSE AMP
SENSE AMP
I/O GATE
&
MASK LOGIC
COCLOCULOMULNMUNMDENDCEDOCEDOCEDOREDRER
COLUMN DECODER
ODT CIRCUIT
OUTPUT
DATA
BUFFER
INPUT
DATA
BUFFER
DM0 – DM3
DATA
STROBE
GENERATOR
DQS0 – DQS3,
DQS0 – DQS3
Notes:
1.) An: n = no. of address pins – 1
2 Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
06/07/2012
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